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Wed, 13 Jan 2021 19:58:43 -0800 (PST) Received: from localhost ([1.132.230.89]) by smtp.gmail.com with ESMTPSA id x1sm3787940pfc.112.2021.01.13.19.58.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Jan 2021 19:58:42 -0800 (PST) Date: Thu, 14 Jan 2021 13:58:35 +1000 From: Nicholas Piggin Subject: Re: [PATCH v5 17/21] powerpc/64: entry cpu time accounting in C To: Christophe Leroy , linuxppc-dev@lists.ozlabs.org References: <20210113073215.516986-1-npiggin@gmail.com> <20210113073215.516986-18-npiggin@gmail.com> <3304762a-d6d6-df70-5546-e7e4dc2d3380@csgroup.eu> In-Reply-To: <3304762a-d6d6-df70-5546-e7e4dc2d3380@csgroup.eu> MIME-Version: 1.0 Message-Id: <1610596381.is1o9lsf5s.astroid@bobo.none> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Excerpts from Christophe Leroy's message of January 14, 2021 1:05 am: >=20 >=20 > Le 13/01/2021 =C3=A0 08:32, Nicholas Piggin a =C3=A9crit=C2=A0: >> There is no need for this to be in asm, use the new intrrupt entry wrapp= er. >>=20 >> Signed-off-by: Nicholas Piggin >> --- >> arch/powerpc/include/asm/interrupt.h | 7 +++++++ >> arch/powerpc/include/asm/ppc_asm.h | 24 ------------------------ >> arch/powerpc/kernel/exceptions-64e.S | 1 - >> arch/powerpc/kernel/exceptions-64s.S | 5 ----- >> 4 files changed, 7 insertions(+), 30 deletions(-) >>=20 >> diff --git a/arch/powerpc/include/asm/interrupt.h b/arch/powerpc/include= /asm/interrupt.h >> index 6eba7c489753..e278dffe7657 100644 >> --- a/arch/powerpc/include/asm/interrupt.h >> +++ b/arch/powerpc/include/asm/interrupt.h >> @@ -4,6 +4,7 @@ >> =20 >> #include >> #include >> +#include >> #include >> =20 >> struct interrupt_state { >> @@ -25,6 +26,9 @@ static inline void interrupt_enter_prepare(struct pt_r= egs *regs, struct interrup >> if (user_mode(regs)) { >> CT_WARN_ON(ct_state() !=3D CONTEXT_USER); >> user_exit_irqoff(); >> + >> + account_cpu_user_entry(); >=20 > Are interrupts still disabled here ? Otherwise you risk getting IRQ time = accounted on user. Yes. Only the handlers themselves will enable interrupts, with interrupt_cond_local_irq_enable. >=20 >> + account_stolen_time(); >> } else { >> /* >> * CT_WARN_ON comes here via program_check_exception, >> @@ -38,6 +42,9 @@ static inline void interrupt_enter_prepare(struct pt_r= egs *regs, struct interrup >> #ifdef CONFIG_PPC_BOOK3E_64 >> state->ctx_state =3D exception_enter(); >> #endif >> + >> + if (!IS_ENABLED(CONFIG_PPC_BOOK3S_64) && user_mode(regs)) >> + account_cpu_user_entry(); >=20 > Isn't this interrupt_enter_prepare() function called also on PPC32 ? > Have you removed the ACCOUNT_CPU_USER_ENTRY() from entry_32.S ? Yes and no, I was thinking of 64 only :( I can make that for 64E. 32-bit could be another patch if you want it. Thanks, Nick