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Thu, 01 Apr 2021 00:36:12 -0700 (PDT) Received: from localhost ([1.132.246.127]) by smtp.gmail.com with ESMTPSA id i10sm5328468pgo.75.2021.04.01.00.36.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Apr 2021 00:36:11 -0700 (PDT) Date: Thu, 01 Apr 2021 17:36:06 +1000 From: Nicholas Piggin Subject: Re: [PATCH] powerpc/64s: power4 nap fixup in C To: Michael Ellerman , Andreas Schwab References: <20210312012044.3660743-1-npiggin@gmail.com> <87y2e6fu7v.fsf__9754.75274478725$1616992871$gmane$org@mpe.ellerman.id.au> <87v99aj7tr.fsf__47134.2879392736$1617031867$gmane$org@igel.home> <87r1jyj5e1.fsf@igel.home> In-Reply-To: <87r1jyj5e1.fsf@igel.home> MIME-Version: 1.0 Message-Id: <1617262357.w4yq2kiecw.astroid@bobo.none> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Excerpts from Andreas Schwab's message of March 30, 2021 2:23 am: > On M=C3=A4r 29 2021, Andreas Schwab wrote: >=20 >> On M=C3=A4r 29 2021, Michael Ellerman wrote: >> >>> Nicholas Piggin writes: >>>> There is no need for this to be in asm, use the new intrrupt entry wra= pper. >>>> >>>> Signed-off-by: Nicholas Piggin >>>> --- >>>> Hopefully this works on a real G5 now, but I couldn't reproduce the >>>> problem with QEMU. >>> >>> It still prevents my G5 from booting. >> >> I see differing failures. What's common is that there is a pause of >> about 60 seconds before the crash occurs. It looks like the crash >> occurs in power4_idle_nap+0x30/0x34. Unfortuately, the BootX console is >> too small to see enough. >=20 > I was now able to see the messages on the VGA console, and the problem > is actually that the cpus are starting to stall. This is strange, I haven't been able to figure out what is wrong. I've been looking at QEMU code and now I'll have to try find a POWER4/5 or PPC970 manual to see what exactly this MSR[POW] thing does and make=20 sure QEMU matches it. Progress might be slow. Worst case I guess we revert if it can't be fixed before next merge window. Thanks, Nick