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Wed, 07 Apr 2021 05:13:32 -0700 (PDT) Received: from localhost ([1.132.149.34]) by smtp.gmail.com with ESMTPSA id m9sm21723581pgt.65.2021.04.07.05.13.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Apr 2021 05:13:31 -0700 (PDT) Date: Wed, 07 Apr 2021 22:13:22 +1000 From: Nicholas Piggin Subject: Re: [PATCH] powerpc/powernv: Enable HAIL (HV AIL) for ISA v3.1 processors To: linuxppc-dev@lists.ozlabs.org, Michael Ellerman References: <20210402024124.545826-1-npiggin@gmail.com> <87v98ye3cn.fsf@mpe.ellerman.id.au> In-Reply-To: <87v98ye3cn.fsf@mpe.ellerman.id.au> MIME-Version: 1.0 Message-Id: <1617797140.zqn9fqbd4y.astroid@bobo.none> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Excerpts from Michael Ellerman's message of April 7, 2021 9:33 pm: > Nicholas Piggin writes: >> Starting with ISA v3.1, LPCR[AIL] no longer controls the interrupt >> mode for HV=3D1 interrupts. Instead, a new LPCR[HAIL] bit is defined >> which behaves like AIL=3D3 for HV interrupts when set. >> >> Set HAIL on bare metal to give us mmu-on interrupts and improve >> performance. >> >> This also fixes an scv bug: we don't implement scv real mode (AIL=3D0) >> vectors because they are at an inconvenient location, so we just >> disable scv support when AIL can not be set. However powernv assumes >> that LPCR[AIL] will enable AIL mode so it enables scv support despite >> HV interrupts being AIL=3D0, which causes scv interrupts to go off into >> the weeds. >=20 > Should we tag this as fixing the initial P10 support, or the scv > support? Or neither? Good question. It does fix a nasty crash with scv so at least it should be tagged I guess. I don't know of anything else that assumes AIL on bare metal, so I don't=20 know of a crashy bug it fixes with initial P10 support. But it is a bit=20 odd for a HV OS running a v3.1 processor to set the old LPCR AIL bits,=20 so it is some kind of bug fix (performance at least). Could go either way I guess. Thanks, Nick >=20 > cheers >=20 >> diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/r= eg.h >> index 1be20bc8dce2..9086a2644c89 100644 >> --- a/arch/powerpc/include/asm/reg.h >> +++ b/arch/powerpc/include/asm/reg.h >> @@ -441,6 +441,7 @@ >> #define LPCR_VRMA_LP1 ASM_CONST(0x0000800000000000) >> #define LPCR_RMLS 0x1C000000 /* Implementation dependent RMO limit s= el */ >> #define LPCR_RMLS_SH 26 >> +#define LPCR_HAIL ASM_CONST(0x0000000004000000) /* HV AIL (ISAv3.1= ) */ >> #define LPCR_ILE ASM_CONST(0x0000000002000000) /* !HV irqs set MSR= :LE */ >> #define LPCR_AIL ASM_CONST(0x0000000001800000) /* Alternate interrup= t location */ >> #define LPCR_AIL_0 ASM_CONST(0x0000000000000000) /* MMU off exceptio= n offset 0x0 */ >> diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_= 64.c >> index 04a31586f760..671192afcdfd 100644 >> --- a/arch/powerpc/kernel/setup_64.c >> +++ b/arch/powerpc/kernel/setup_64.c >> @@ -233,10 +233,23 @@ static void cpu_ready_for_interrupts(void) >> * If we are not in hypervisor mode the job is done once for >> * the whole partition in configure_exceptions(). >> */ >> - if (cpu_has_feature(CPU_FTR_HVMODE) && >> - cpu_has_feature(CPU_FTR_ARCH_207S)) { >> + if (cpu_has_feature(CPU_FTR_HVMODE)) { >> unsigned long lpcr =3D mfspr(SPRN_LPCR); >> - mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3); >> + unsigned long new_lpcr =3D lpcr; >> + >> + if (cpu_has_feature(CPU_FTR_ARCH_31)) { >> + /* P10 DD1 does not have HAIL */ >> + if (pvr_version_is(PVR_POWER10) && >> + (mfspr(SPRN_PVR) & 0xf00) =3D=3D 0x100) >> + new_lpcr |=3D LPCR_AIL_3; >> + else >> + new_lpcr |=3D LPCR_HAIL; >> + } else if (cpu_has_feature(CPU_FTR_ARCH_207S)) { >> + new_lpcr |=3D LPCR_AIL_3; >> + } >> + >> + if (new_lpcr !=3D lpcr) >> + mtspr(SPRN_LPCR, new_lpcr); >> } >> =20 >> /* >> --=20 >> 2.23.0 >=20