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Date: Sat, 10 Apr 2021 10:39:12 +1000
From: Nicholas Piggin <npiggin@gmail.com>
Subject: Re: [PATCH v6 32/48] KVM: PPC: Book3S HV P9: Read machine check
 registers while MSR[RI] is 0
To: Alexey Kardashevskiy <aik@ozlabs.ru>, kvm-ppc@vger.kernel.org
References: <20210405011948.675354-1-npiggin@gmail.com>
 <20210405011948.675354-33-npiggin@gmail.com>
 <0adc89d0-c765-d11b-ffe4-cbbf2f8f9c49@ozlabs.ru>
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Excerpts from Alexey Kardashevskiy's message of April 9, 2021 6:55 pm:
>=20
>=20
> On 05/04/2021 11:19, Nicholas Piggin wrote:
>> SRR0/1, DAR, DSISR must all be protected from machine check which can
>> clobber them. Ensure MSR[RI] is clear while they are live.
>>=20
>> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
>> ---
>>   arch/powerpc/kvm/book3s_hv.c           | 11 +++++++--
>>   arch/powerpc/kvm/book3s_hv_interrupt.c | 33 +++++++++++++++++++++++---
>>   arch/powerpc/kvm/book3s_hv_ras.c       |  2 ++
>>   3 files changed, 41 insertions(+), 5 deletions(-)
>>=20
>> diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
>> index d6eecedaa5a5..5f0ac6567a06 100644
>> --- a/arch/powerpc/kvm/book3s_hv.c
>> +++ b/arch/powerpc/kvm/book3s_hv.c
>> @@ -3567,11 +3567,16 @@ static int kvmhv_p9_guest_entry(struct kvm_vcpu =
*vcpu, u64 time_limit,
>>   	mtspr(SPRN_BESCR, vcpu->arch.bescr);
>>   	mtspr(SPRN_WORT, vcpu->arch.wort);
>>   	mtspr(SPRN_TIDR, vcpu->arch.tid);
>> -	mtspr(SPRN_DAR, vcpu->arch.shregs.dar);
>> -	mtspr(SPRN_DSISR, vcpu->arch.shregs.dsisr);
>>   	mtspr(SPRN_AMR, vcpu->arch.amr);
>>   	mtspr(SPRN_UAMOR, vcpu->arch.uamor);
>>  =20
>> +	/*
>> +	 * DAR, DSISR, and for nested HV, SPRGs must be set with MSR[RI]
>> +	 * clear (or hstate set appropriately to catch those registers
>> +	 * being clobbered if we take a MCE or SRESET), so those are done
>> +	 * later.
>> +	 */
>> +
>>   	if (!(vcpu->arch.ctrl & 1))
>>   		mtspr(SPRN_CTRLT, mfspr(SPRN_CTRLF) & ~1);
>>  =20
>> @@ -3614,6 +3619,8 @@ static int kvmhv_p9_guest_entry(struct kvm_vcpu *v=
cpu, u64 time_limit,
>>   			hvregs.vcpu_token =3D vcpu->vcpu_id;
>>   		}
>>   		hvregs.hdec_expiry =3D time_limit;
>> +		mtspr(SPRN_DAR, vcpu->arch.shregs.dar);
>> +		mtspr(SPRN_DSISR, vcpu->arch.shregs.dsisr);
>>   		trap =3D plpar_hcall_norets(H_ENTER_NESTED, __pa(&hvregs),
>>   					  __pa(&vcpu->arch.regs));
>>   		kvmhv_restore_hv_return_state(vcpu, &hvregs);
>> diff --git a/arch/powerpc/kvm/book3s_hv_interrupt.c b/arch/powerpc/kvm/b=
ook3s_hv_interrupt.c
>> index 6fdd93936e16..e93d2a6456ff 100644
>> --- a/arch/powerpc/kvm/book3s_hv_interrupt.c
>> +++ b/arch/powerpc/kvm/book3s_hv_interrupt.c
>> @@ -132,6 +132,7 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 t=
ime_limit, unsigned long lpc
>>   	s64 hdec;
>>   	u64 tb, purr, spurr;
>>   	u64 *exsave;
>> +	bool ri_set;
>>   	unsigned long msr =3D mfmsr();
>>   	int trap;
>>   	unsigned long host_hfscr =3D mfspr(SPRN_HFSCR);
>> @@ -203,9 +204,6 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 t=
ime_limit, unsigned long lpc
>>   	 */
>>   	mtspr(SPRN_HDEC, hdec);
>>  =20
>> -	mtspr(SPRN_SRR0, vcpu->arch.shregs.srr0);
>> -	mtspr(SPRN_SRR1, vcpu->arch.shregs.srr1);
>> -
>>   	start_timing(vcpu, &vcpu->arch.rm_entry);
>>  =20
>>   	vcpu->arch.ceded =3D 0;
>> @@ -231,6 +229,13 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 =
time_limit, unsigned long lpc
>>   	 */
>>   	mtspr(SPRN_HDSISR, HDSISR_CANARY);
>>  =20
>> +	__mtmsrd(0, 1); /* clear RI */
>> +
>> +	mtspr(SPRN_DAR, vcpu->arch.shregs.dar);
>> +	mtspr(SPRN_DSISR, vcpu->arch.shregs.dsisr);
>> +	mtspr(SPRN_SRR0, vcpu->arch.shregs.srr0);
>> +	mtspr(SPRN_SRR1, vcpu->arch.shregs.srr1);
>> +
>>   	accumulate_time(vcpu, &vcpu->arch.guest_time);
>>  =20
>>   	local_paca->kvm_hstate.in_guest =3D KVM_GUEST_MODE_GUEST_HV_FAST;
>> @@ -248,7 +253,13 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 =
time_limit, unsigned long lpc
>>  =20
>>   	/* 0x2 bit for HSRR is only used by PR and P7/8 HV paths, clear it */
>>   	trap =3D local_paca->kvm_hstate.scratch0 & ~0x2;
>> +
>> +	/* HSRR interrupts leave MSR[RI] unchanged, SRR interrupts clear it. *=
/
>> +	ri_set =3D false;
>>   	if (likely(trap > BOOK3S_INTERRUPT_MACHINE_CHECK)) {
>> +		if (trap !=3D BOOK3S_INTERRUPT_SYSCALL &&
>> +				(vcpu->arch.shregs.msr & MSR_RI))
>> +			ri_set =3D true;
>>   		exsave =3D local_paca->exgen;
>>   	} else if (trap =3D=3D BOOK3S_INTERRUPT_SYSTEM_RESET) {
>>   		exsave =3D local_paca->exnmi;
>> @@ -258,6 +269,22 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 =
time_limit, unsigned long lpc
>>  =20
>>   	vcpu->arch.regs.gpr[1] =3D local_paca->kvm_hstate.scratch1;
>>   	vcpu->arch.regs.gpr[3] =3D local_paca->kvm_hstate.scratch2;
>> +
>> +	/*
>> +	 * Only set RI after reading machine check regs (DAR, DSISR, SRR0/1)
>> +	 * and hstate scratch (which we need to move into exsave to make
>> +	 * re-entrant vs SRESET/MCE)
>> +	 */
>> +	if (ri_set) {
>> +		if (unlikely(!(mfmsr() & MSR_RI))) {
>> +			__mtmsrd(MSR_RI, 1);
>> +			WARN_ON_ONCE(1);
>> +		}
>> +	} else {
>> +		WARN_ON_ONCE(mfmsr() & MSR_RI);
>> +		__mtmsrd(MSR_RI, 1);
>> +	}
>> +
>>   	vcpu->arch.regs.gpr[9] =3D exsave[EX_R9/sizeof(u64)];
>>   	vcpu->arch.regs.gpr[10] =3D exsave[EX_R10/sizeof(u64)];
>>   	vcpu->arch.regs.gpr[11] =3D exsave[EX_R11/sizeof(u64)];
>> diff --git a/arch/powerpc/kvm/book3s_hv_ras.c b/arch/powerpc/kvm/book3s_=
hv_ras.c
>> index d4bca93b79f6..8d8a4d5f0b55 100644
>> --- a/arch/powerpc/kvm/book3s_hv_ras.c
>> +++ b/arch/powerpc/kvm/book3s_hv_ras.c
>> @@ -199,6 +199,8 @@ static void kvmppc_tb_resync_done(void)
>>    * know about the exact state of the TB value. Resync TB call will
>>    * restore TB to host timebase.
>>    *
>> + * This could use the new OPAL_HANDLE_HMI2 to avoid resyncing TB every =
time.
>=20
>=20
> Educating myself - is it because OPAL_HANDLE_HMI2 tells if it is TB/TOD=20
> which is the problem so we can avoid calling opal_resync_timebase() if=20
> it is not TB?

Yes.

> OPAL_HANDLE_HMI2 does not seem to resync TB itself. The=20
> comment just does not seem related to the rest of the patch.

Yeah it's not related, I'll take it out.

>=20
> Otherwise, looks good.
>=20
> Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>

Thanks,
Nick