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Rao" Subject: Re: [PATCH 1/2] powerpc/sstep: Add emulation support for =?CP1251?B?kXNldGKS?= instruction To: Daniel Axtens , linuxppc-dev@lists.ozlabs.org, Sathvika Vasireddy References: <767e53c4c27da024ca277e21ffcd0cff131f5c73.1618469454.git.sathvika@linux.vnet.ibm.com> <875z0mfzbf.fsf@linkitivity.dja.id.au> In-Reply-To: <875z0mfzbf.fsf@linkitivity.dja.id.au> MIME-Version: 1.0 User-Agent: astroid/v0.15-23-gcdc62b30 (https://github.com/astroidmail/astroid) Message-Id: <1618899164.u2uju6vw3c.naveen@linux.ibm.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: W8TiEXg0FtDlv9KPqp5YiZOMLBGxxsvk X-Proofpoint-GUID: W8TiEXg0FtDlv9KPqp5YiZOMLBGxxsvk X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-04-20_01:2021-04-19, 2021-04-20 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 mlxlogscore=999 mlxscore=0 adultscore=0 suspectscore=0 spamscore=0 impostorscore=0 priorityscore=1501 clxscore=1011 phishscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104060000 definitions=main-2104200046 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Daniel Axtens wrote: > Sathvika Vasireddy writes: >=20 >> This adds emulation support for the following instruction: >> * Set Boolean (setb) >> >> Signed-off-by: Sathvika Vasireddy >> --- >> arch/powerpc/lib/sstep.c | 12 ++++++++++++ >> 1 file changed, 12 insertions(+) >> >> diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c >> index c6aebc149d14..263c613d7490 100644 >> --- a/arch/powerpc/lib/sstep.c >> +++ b/arch/powerpc/lib/sstep.c >> @@ -1964,6 +1964,18 @@ int analyse_instr(struct instruction_op *op, cons= t struct pt_regs *regs, >> op->val =3D ~(regs->gpr[rd] | regs->gpr[rb]); >> goto logical_done; >> =20 >> + case 128: /* setb */ >> + if (!cpu_has_feature(CPU_FTR_ARCH_300)) >> + goto unknown_opcode; >=20 > Ok, if I've understood correctly... >=20 >> + ra =3D ra & ~0x3; >=20 > This masks off the bits of RA that are not part of BTF: >=20 > ra is in [0, 31] which is [0b00000, 0b11111] > Then ~0x3 =3D ~0b00011 > ra =3D ra & 0b11100 >=20 > This gives us then, > ra =3D btf << 2; or > btf =3D ra >> 2; >=20 > Let's then check to see if your calculations read the right fields. >=20 >> + if ((regs->ccr) & (1 << (31 - ra))) >> + op->val =3D -1; >> + else if ((regs->ccr) & (1 << (30 - ra))) >> + op->val =3D 1; >> + else >> + op->val =3D 0; >=20 >=20 > CR field: 7 6 5 4 3 2 1 0 > bit: 0123 0123 0123 0123 0123 0123 0123 0123 > normal bit #: 0.....................................31 > ibm bit #: 31.....................................0 >=20 > If btf =3D 0, ra =3D 0, check normal bits 31 and 30, which are both in CR= 0. > CR field: 7 6 5 4 3 2 1 0 > bit: 0123 0123 0123 0123 0123 0123 0123 0123 > ^^ >=20 > If btf =3D 7, ra =3D 0b11100 =3D 28, so check normal bits 31-28 and 30-28= , > which are 3 and 2. >=20 > CR field: 7 6 5 4 3 2 1 0 > bit: 0123 0123 0123 0123 0123 0123 0123 0123 > ^^ >=20 > If btf =3D 3, ra =3D 0b01100 =3D 12, for normal bits 19 and 18: >=20 > CR field: 7 6 5 4 3 2 1 0 > bit: 0123 0123 0123 0123 0123 0123 0123 0123 > ^^ >=20 > So yes, your calculations, while I struggle to follow _how_ they work, > do in fact seem to work. >=20 > Checkpatch does have one complaint: >=20 > CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 'regs->ccr' > #30: FILE: arch/powerpc/lib/sstep.c:1971: > + if ((regs->ccr) & (1 << (31 - ra))) >=20 > I don't really mind the parenteses: I think you are safe to ignore > checkpatch here unless someone else complains :) >=20 > If you do end up respinning the patch, I think it would be good to make > the maths a bit clearer. I think it works because a left shift of 2 is > the same as multiplying by 4, but it would be easier to follow if you > used a temporary variable for btf. Indeed. I wonder if it is better to follow the ISA itself. Per the ISA,=20 the bit we are interested in is: 4 x BFA + 32 So, if we use that along with the PPC_BIT() macro, we get: if (regs->ccr & PPC_BIT(ra + 32)) >> + goto compute_done; >> + I can see why you thought this should be in the section with other=20 logical instructions. However, since this instruction does not modify CR=20 itself, this is probably better placed earlier -- somewhere near 'mfcr'=20 instruction emulation. - Naveen