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Rao" Subject: Re: [PATCH 1/2] powerpc/sstep: Add emulation support for =?CP1251?B?kXNldGKS?= instruction To: Daniel Axtens , linuxppc-dev@lists.ozlabs.org, Michael Ellerman , Sathvika Vasireddy References: <767e53c4c27da024ca277e21ffcd0cff131f5c73.1618469454.git.sathvika@linux.vnet.ibm.com> <875z0mfzbf.fsf@linkitivity.dja.id.au> <1618899164.u2uju6vw3c.naveen@linux.ibm.com> <87lf9caycg.fsf@mpe.ellerman.id.au> <1619085028.flue8xv2n9.naveen@linux.ibm.com> <87bla5b041.fsf@mpe.ellerman.id.au> In-Reply-To: <87bla5b041.fsf@mpe.ellerman.id.au> MIME-Version: 1.0 User-Agent: astroid/v0.15-23-gcdc62b30 (https://github.com/astroidmail/astroid) Message-Id: <1619541277.598mrhcod5.naveen@linux.ibm.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 8Kk7kE1B0i6MqKJDC0wlDEdgH0STf2fl X-Proofpoint-GUID: 8Kk7kE1B0i6MqKJDC0wlDEdgH0STf2fl X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-04-27_10:2021-04-27, 2021-04-27 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 adultscore=0 mlxlogscore=999 clxscore=1015 priorityscore=1501 impostorscore=0 mlxscore=0 suspectscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104060000 definitions=main-2104270112 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Michael Ellerman wrote: > "Naveen N. Rao" writes: >> Michael Ellerman wrote: >>> "Naveen N. Rao" writes: >>>> Daniel Axtens wrote: >>>>> Sathvika Vasireddy writes: >>>>>=20 >>>>>> This adds emulation support for the following instruction: >>>>>> * Set Boolean (setb) >>>>>> >>>>>> Signed-off-by: Sathvika Vasireddy >>> ... >>>>>=20 >>>>> If you do end up respinning the patch, I think it would be good to ma= ke >>>>> the maths a bit clearer. I think it works because a left shift of 2 i= s >>>>> the same as multiplying by 4, but it would be easier to follow if you >>>>> used a temporary variable for btf. >>>> >>>> Indeed. I wonder if it is better to follow the ISA itself. Per the ISA= ,=20 >>>> the bit we are interested in is: >>>> 4 x BFA + 32 >>>> >>>> So, if we use that along with the PPC_BIT() macro, we get: >>>> if (regs->ccr & PPC_BIT(ra + 32)) >>>=20 >>> Use of PPC_BIT risks annoying your maintainer :) >> >> Uh oh... that isn't good :) >> >> I looked up previous discussions and I think I now understand why you=20 >> don't prefer it. >=20 > Hah, I'd forgotten I'd written (ranted :D) about this in the past. >=20 >> But, I feel it helps make it easy to follow the code when referring to=20 >> the ISA. >=20 > That's true. But I think that's much much less common than people > reading the code in isolation. I thought that isn't so for at least the instruction emulation=20 infrastructure... >=20 > And ultimately it doesn't matter if the code (appears to) match the ISA, > it matters that the code works. My worry is that too much use of those > type of macros obscures what's actually happening. ... but, I agree on the above point. I can see why it is better to keep=20 it simple. I also see precedence for what both you and Segher are suggesting in the=20 existing code in sstep.c >=20 >> I'm wondering if it is just the name you dislike and if so,=20 >> does it make sense to rename PPC_BIT() to something else? We have=20 >> BIT_ULL(), so perhaps BIT_MSB_ULL() or MSB_BIT_ULL()? >=20 > The name is part of it. But I don't really like BIT_ULL() either, it > hides in a macro something that could just be there in front of you > ie. (1ull << x). >=20 >=20 > For this case of setb, I think I'd go with something like below. It > doesn't exactly match the ISA, but I think there's minimal obfuscation > of what's actually going on. >=20 > // ra is now bfa > ra =3D (ra >> 2); >=20 > // Extract 4-bit CR field > val =3D regs->ccr >> (CR0_SHIFT - 4 * ra); >=20 > if (val & 8) > op->val =3D -1; > else if (val & 4) > op->val =3D 1; > else > op->val =3D 0; >=20 >=20 > If anything could use a macro it would be the 8 and 4, eg. CR_LT, CR_GT. >=20 > Of course that's probably got a bug in it, because I just wrote it by > eye and it's 11:28 pm :) LGTM, thanks. I'll let Sathvika decide on which variant she wants to go=20 with for v2 :) - Naveen