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From: Shengjiu Wang <shengjiu.wang@nxp.com>
To: nicoleotsuka@gmail.com, Xiubo.Lee@gmail.com, festevam@gmail.com,
	shengjiu.wang@gmail.com, lgirdwood@gmail.com, broonie@kernel.org,
	perex@perex.cz, tiwai@suse.com, alsa-devel@alsa-project.org,
	robh+dt@kernel.org, krzk+dt@kernel.org,
	devicetree@vger.kernel.org
Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org
Subject: [PATCH 5/6] ASoC: dt-bindings: fsl_spdif: Add two PLL clock source
Date: Thu, 30 Jun 2022 13:39:13 +0800	[thread overview]
Message-ID: <1656567554-32122-6-git-send-email-shengjiu.wang@nxp.com> (raw)
In-Reply-To: <1656567554-32122-1-git-send-email-shengjiu.wang@nxp.com>

Add two PLL clock source, they are the parent clocks of root clock
one is for 8kHz series rates, another one is for 11kHz series rates.
They are optional clocks, if there are such clocks, then driver
can switch between them for supporting more accurate rates.

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
---
 Documentation/devicetree/bindings/sound/fsl,spdif.yaml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/sound/fsl,spdif.yaml b/Documentation/devicetree/bindings/sound/fsl,spdif.yaml
index f226ec13167a..1d64e8337aa4 100644
--- a/Documentation/devicetree/bindings/sound/fsl,spdif.yaml
+++ b/Documentation/devicetree/bindings/sound/fsl,spdif.yaml
@@ -58,6 +58,8 @@ properties:
           slave of the Shared Peripheral Bus and when two or more bus masters
           (CPU, DMA or DSP) try to access it. This property is optional depending
           on the SoC design.
+      - description: PLL clock source for 8kHz series rate, optional.
+      - description: PLL clock source for 11khz series rate, optional.
     minItems: 9
 
   clock-names:
@@ -72,6 +74,8 @@ properties:
       - const: rxtx6
       - const: rxtx7
       - const: spba
+      - const: pll8k
+      - const: pll11k
     minItems: 9
 
   big-endian:
-- 
2.17.1


  parent reply	other threads:[~2022-06-30  5:56 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-30  5:39 [PATCH 0/6] Add support of two Audio PLL source Shengjiu Wang
2022-06-30  5:39 ` [PATCH 1/6] ASoC: fsl_utils: Add function to handle PLL clock source Shengjiu Wang
2022-06-30  5:39 ` [PATCH 2/6] ASoC: fsl_spdif: Add support for PLL switch at runtime Shengjiu Wang
2022-06-30  5:39 ` [PATCH 3/6] ASoC: fsl_micfil: " Shengjiu Wang
2022-06-30 10:37   ` Mark Brown
2022-06-30 12:15     ` Shengjiu Wang
2022-06-30  5:39 ` [PATCH 4/6] ASoC: fsl_sai: " Shengjiu Wang
2022-06-30  5:39 ` Shengjiu Wang [this message]
2022-06-30  5:39 ` [PATCH 6/6] ASoC: dt-bindings: fsl-sai: Add two PLL clock source Shengjiu Wang

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