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From: "Gerhard Pircher" <gerhard_pircher@gmx.net>
To: benh@kernel.crashing.org, linuxppc-dev@ozlabs.org
Cc: kumar.gala@freescale.com, paulus@samba.org
Subject: [PATCH] powerpc/mm: Fix handling of _PAGE_COHERENT in BAT setup code
Date: Fri, 23 Jan 2009 17:51:28 +0100	[thread overview]
Message-ID: <20090123165128.74270@gmx.net> (raw)
In-Reply-To: <20090118202943.85450@gmx.net>

_PAGE_COHERENT is now always set in _PAGE_RAM resp. PAGE_KERNEL.
Thus it has to be masked out, if the BAT mapping should be non
cacheable or CPU_FTR_NEED_COHERENT is not set.

Signed-off-by: Gerhard Pircher <gerhard_pircher@gmx.net>
---
 arch/powerpc/mm/ppc_mmu_32.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/powerpc/mm/ppc_mmu_32.c b/arch/powerpc/mm/ppc_mmu_32.c
index 45d9253..fe65c40 100644
--- a/arch/powerpc/mm/ppc_mmu_32.c
+++ b/arch/powerpc/mm/ppc_mmu_32.c
@@ -123,9 +123,9 @@ void __init setbat(int index, unsigned long virt, phys_addr_t phys,
 	int wimgxpp;
 	struct ppc_bat *bat = BATS[index];
 
-	if (((flags & _PAGE_NO_CACHE) == 0) &&
-	    cpu_has_feature(CPU_FTR_NEED_COHERENT))
-		flags |= _PAGE_COHERENT;
+	if ((flags & _PAGE_NO_CACHE) ||
+	    (cpu_has_feature(CPU_FTR_NEED_COHERENT) == 0))
+		flags &= ~_PAGE_COHERENT;
 
 	bl = (size >> 17) - 1;
 	if (PVR_VER(mfspr(SPRN_PVR)) != 1) {
-- 
1.5.3.4


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  reply	other threads:[~2009-01-23 16:51 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2008-12-19  5:13 [PATCH 0/10] powerpc: Preliminary work to enable SMP BookE (v3) Benjamin Herrenschmidt
2008-12-19  5:13 ` [PATCH 1/10] powerpc/4xx: Extended DCR support v2 Benjamin Herrenschmidt
2008-12-19 12:36   ` Josh Boyer
2008-12-19  5:13 ` [PATCH 2/10] powerpc/mm: Split mmu_context handling v3 Benjamin Herrenschmidt
2008-12-19  5:13 ` [PATCH 3/10] powerpc/mm: Rework context management for CPUs with no hash table v2 Benjamin Herrenschmidt
2008-12-19  5:13 ` [PATCH 4/10] powerpc/mm: Introduce MMU features v3 Benjamin Herrenschmidt
2008-12-19  5:13 ` [PATCH 5/10] powerpc/mm: Add SMP support to no-hash TLB handling v5 Benjamin Herrenschmidt
2008-12-19  5:13 ` [PATCH 6/10] powerpc/mm: Split low level tlb invalidate for nohash processors Benjamin Herrenschmidt
2008-12-19  5:13 ` [PATCH 7/10] powerpc/44x: No need to mask MSR:CE, ME or DE in _tlbil_va on 440 Benjamin Herrenschmidt
2008-12-19 12:37   ` [PATCH 7/10] powerpc/44x: No need to mask MSR:CE,ME " Josh Boyer
2008-12-19  5:13 ` [PATCH 8/10] powerpc/mm: Runtime allocation of mmu context maps for nohash CPUs v2 Benjamin Herrenschmidt
2008-12-19  5:13 ` [PATCH 9/10] powerpc/mm: Rework usage of _PAGE_COHERENT/NO_CACHE/GUARDED v2 Benjamin Herrenschmidt
2009-01-18 19:43   ` Gerhard Pircher
2009-01-18 19:55     ` Benjamin Herrenschmidt
2009-01-18 20:29       ` Gerhard Pircher
2009-01-23 16:51         ` Gerhard Pircher [this message]
2008-12-19  5:13 ` [PATCH 10/10] powerpc/44x: 44x TLB doesn't need "Guarded" set for all pages Benjamin Herrenschmidt
2008-12-19 12:38   ` Josh Boyer
2008-12-19 16:05 ` [PATCH 0/10] powerpc: Preliminary work to enable SMP BookE (v3) Kumar Gala

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