From: Rex Feany <RFeany@mrv.com>
To: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: linuxppc-dev@ozlabs.org
Subject: [PATCH] powerpc/8xx: fix regression introduced by cache coherency rewrite
Date: Wed, 23 Sep 2009 17:45:52 -0700 [thread overview]
Message-ID: <20090924004552.GA11737@compile2.chatsunix.int.mrv.com> (raw)
After upgrading to the latest kernel on my mpc875 userspace started
running incredibly slow (hours to get to a shell, even!).
I tracked it down to commit 8d30c14cab30d405a05f2aaceda1e9ad57800f36,
that patch removed a work-around for the 8xx. Adding it
back makes my problem go away.
Signed-off-by: Rex Feany <rfeany@mrv.com>
diff --git a/arch/powerpc/mm/pgtable.c b/arch/powerpc/mm/pgtable.c
index 627767d..d8e6725 100644
--- a/arch/powerpc/mm/pgtable.c
+++ b/arch/powerpc/mm/pgtable.c
@@ -30,6 +30,8 @@
#include <asm/tlbflush.h>
#include <asm/tlb.h>
+#include "mmu_decl.h"
+
static DEFINE_PER_CPU(struct pte_freelist_batch *, pte_freelist_cur);
static unsigned long pte_freelist_forced_free;
@@ -119,7 +121,7 @@ void pte_free_finish(void)
/*
* Handle i/d cache flushing, called from set_pte_at() or ptep_set_access_flags()
*/
-static pte_t do_dcache_icache_coherency(pte_t pte)
+static pte_t do_dcache_icache_coherency(pte_t pte, unsigned long addr)
{
unsigned long pfn = pte_pfn(pte);
struct page *page;
@@ -128,6 +130,17 @@ static pte_t do_dcache_icache_coherency(pte_t pte)
return pte;
page = pfn_to_page(pfn);
+#ifdef CONFIG_8xx
+ /* On 8xx, cache control instructions (particularly
+ * "dcbst" from flush_dcache_icache) fault as write
+ * operation if there is an unpopulated TLB entry
+ * for the address in question. To workaround that,
+ * we invalidate the TLB here, thus avoiding dcbst
+ * misbehaviour.
+ */
+ _tlbil_va(addr, 0 /* 8xx doesn't care about PID */);
+#endif
+
if (!PageReserved(page) && !test_bit(PG_arch_1, &page->flags)) {
pr_devel("do_dcache_icache_coherency... flushing\n");
flush_dcache_icache_page(page);
@@ -198,7 +211,7 @@ void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pte
*/
pte = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS);
if (pte_need_exec_flush(pte, 1))
- pte = do_dcache_icache_coherency(pte);
+ pte = do_dcache_icache_coherency(pte, addr);
/* Perform the setting of the PTE */
__set_pte_at(mm, addr, ptep, pte, 0);
@@ -216,7 +229,7 @@ int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address,
{
int changed;
if (!dirty && pte_need_exec_flush(entry, 0))
- entry = do_dcache_icache_coherency(entry);
+ entry = do_dcache_icache_coherency(entry, address);
changed = !pte_same(*(ptep), entry);
if (changed) {
if (!(vma->vm_flags & VM_HUGETLB))
next reply other threads:[~2009-09-24 1:00 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-09-24 0:45 Rex Feany [this message]
2009-09-24 6:44 ` [PATCH] powerpc/8xx: fix regression introduced by cache coherency rewrite Benjamin Herrenschmidt
2009-09-24 23:33 ` Rex Feany
2009-09-24 23:52 ` Benjamin Herrenschmidt
2009-09-25 1:35 ` Rex Feany
2009-09-25 1:51 ` Benjamin Herrenschmidt
2009-09-25 3:03 ` Benjamin Herrenschmidt
2009-09-25 8:31 ` Joakim Tjernlund
2009-09-25 9:47 ` Benjamin Herrenschmidt
2009-09-25 10:21 ` Joakim Tjernlund
2009-09-25 21:18 ` Rex Feany
2009-09-27 13:22 ` Joakim Tjernlund
2009-09-28 3:21 ` Benjamin Herrenschmidt
2009-09-28 7:22 ` Joakim Tjernlund
2009-09-28 7:34 ` Benjamin Herrenschmidt
2009-09-28 7:39 ` Joakim Tjernlund
2009-09-28 10:02 ` Joakim Tjernlund
2009-09-29 1:21 ` Rex Feany
2009-09-29 6:26 ` Joakim Tjernlund
2009-09-29 7:07 ` Benjamin Herrenschmidt
2009-09-29 8:13 ` Joakim Tjernlund
2009-09-29 8:16 ` Benjamin Herrenschmidt
2009-09-29 8:24 ` Joakim Tjernlund
2009-09-29 11:56 ` Joakim Tjernlund
2009-09-29 21:03 ` Rex Feany
2009-09-30 7:59 ` Joakim Tjernlund
2009-09-30 8:19 ` Joakim Tjernlund
2009-09-30 9:00 ` Rex Feany
2009-09-30 9:58 ` Joakim Tjernlund
2009-09-30 11:18 ` Joakim Tjernlund
2009-09-30 17:23 ` Joakim Tjernlund
2009-09-30 22:35 ` Benjamin Herrenschmidt
2009-10-01 7:05 ` Joakim Tjernlund
2009-10-02 13:06 ` Joakim Tjernlund
2009-10-02 18:10 ` Joakim Tjernlund
2009-10-02 21:49 ` Scott Wood
2009-10-02 22:04 ` Benjamin Herrenschmidt
2009-10-05 19:28 ` Scott Wood
2009-10-05 20:29 ` Benjamin Herrenschmidt
2009-10-05 21:04 ` Scott Wood
2009-10-03 8:05 ` Joakim Tjernlund
2009-10-03 8:31 ` Benjamin Herrenschmidt
2009-10-03 9:24 ` Joakim Tjernlund
2009-10-03 10:57 ` Benjamin Herrenschmidt
2009-10-03 11:47 ` Joakim Tjernlund
2009-10-04 8:35 ` Joakim Tjernlund
2009-10-04 20:26 ` Benjamin Herrenschmidt
2009-10-04 20:38 ` Joakim Tjernlund
2009-10-05 18:24 ` Scott Wood
2009-10-05 18:50 ` Joakim Tjernlund
2009-10-04 20:10 ` Joakim Tjernlund
2009-10-04 20:28 ` Benjamin Herrenschmidt
2009-10-04 20:45 ` Joakim Tjernlund
2009-10-05 7:28 ` Joakim Tjernlund
2009-10-05 19:16 ` Joakim Tjernlund
2009-10-05 20:28 ` Benjamin Herrenschmidt
2009-09-29 7:07 ` Benjamin Herrenschmidt
2009-09-29 21:09 ` Rex Feany
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20090924004552.GA11737@compile2.chatsunix.int.mrv.com \
--to=rfeany@mrv.com \
--cc=benh@kernel.crashing.org \
--cc=linuxppc-dev@ozlabs.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).