From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mailhub1.si.c-s.fr (pegase1.c-s.fr [93.17.236.30]) by lists.ozlabs.org (Postfix) with ESMTP id 2C9FF1A09D3 for ; Thu, 11 Dec 2014 05:01:16 +1100 (AEDT) From: Christophe Leroy To: Benjamin Herrenschmidt , Paul Mackerras , Michael Ellerman , scottwood@freescale.com Subject: [PATCH 4/4] powerpc32/8xx: invert _PAGE_RW bit in PTE accessors Message-Id: <20141210180046.9A8FA1A5D62@localhost.localdomain> Date: Wed, 10 Dec 2014 19:00:46 +0100 (CET) Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , The 8xx inverts _PAGE_RW. Lets to it in PTE accessors. Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/pte-8xx.h | 1 + arch/powerpc/kernel/head_8xx.S | 3 --- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/powerpc/include/asm/pte-8xx.h b/arch/powerpc/include/asm/pte-8xx.h index daa4616..57bad0a 100644 --- a/arch/powerpc/include/asm/pte-8xx.h +++ b/arch/powerpc/include/asm/pte-8xx.h @@ -57,6 +57,7 @@ #define _PMD_PAGE_8M 0x000c #define _PTE_NONE_MASK _PAGE_KNLRO +#define _PTE_HW_INVERTED _PAGE_RW /* Until my rework is finished, 8xx still needs atomic PTE updates */ #define PTE_ATOMIC_UPDATES 1 diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 3d4b8ee..807b0db 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -441,9 +441,6 @@ DataStoreTLBMiss: and r11, r11, r10 rlwimi r10, r11, 0, _PAGE_PRESENT #endif - /* invert RW */ - xori r10, r10, _PAGE_RW - /* The Linux PTE won't go exactly into the MMU TLB. * Software indicator bits 22 and 28 must be clear. * Software indicator bits 24, 25, 26, and 27 must be -- 2.1.0