From: Scott Wood <oss@buserror.net>
To: Christophe Leroy <christophe.leroy@c-s.fr>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>,
Paul Mackerras <paulus@samba.org>,
Michael Ellerman <mpe@ellerman.id.au>,
linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org
Subject: Re: [v8, 08/23] powerpc/8xx: Map IMMR area with 512k page at a fixed address
Date: Fri, 11 Mar 2016 17:15:39 -0600 [thread overview]
Message-ID: <20160311231539.GB30872@home.buserror.net> (raw)
In-Reply-To: <469ed145e21be6720c186686039b569e30ca1ed4.1455032446.git.christophe.leroy@c-s.fr>
On Tue, Feb 09, 2016 at 05:08:02PM +0100, Christophe Leroy wrote:
> Once the linear memory space has been mapped with 8Mb pages, as
> seen in the related commit, we get 11 millions DTLB missed during
> the reference 600s period. 77% of the misses are on user addresses
> and 23% are on kernel addresses (1 fourth for linear address space
> and 3 fourth for virtual address space)
>
> Traditionaly, each driver manages one computer board which has its
> own components with its own memory maps.
> But on embedded chips like the MPC8xx, the SOC has all registers
> located in the same IO area.
>
> When looking at ioremaps done during startup, we see that
> many drivers are re-mapping small parts of the IMMR for their own use
> and all those small pieces gets their own 4k page, amplifying the
> number of TLB misses: in our system we get 0xff000000 mapped 31 times
> and 0xff003000 mapped 9 times.
>
> Even if each part of IMMR was mapped only once with 4k pages, it would
> still be several small mappings towards linear area.
>
> With the patch, on the same principle as what was done for the RAM,
> the IMMR gets mapped by a 512k page.
"the patch" -- this one, that below says it maps IMMR with other sizes?
>
> In 4k pages mode, we reserve a 4Mb area for mapping IMMR. The TLB
> miss handler checks that we are within the first 512k and bail out
> with page not marked valid if we are outside
>
> In 16k pages mode, it is not realistic to reserve a 64Mb area, so
> we do a standard mapping of the 512k area using 32 pages of 16k.
> The CPM will be mapped via the first two pages, and the SEC engine
> will be mapped via the 16th and 17th pages. As the pages are marked
> guarded, there will be no speculative accesses.
If IMMR is 512k, why do you need to reserve 4M/64M for it?
-Scott
next prev parent reply other threads:[~2016-03-11 23:15 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-09 16:07 [PATCH v8 00/23] powerpc/8xx: Use large pages for RAM and IMMR and other improvments Christophe Leroy
2016-02-09 16:07 ` [PATCH v8 01/23] powerpc/8xx: Save r3 all the time in DTLB miss handler Christophe Leroy
2016-02-09 16:07 ` [PATCH v8 02/23] powerpc/8xx: Map linear kernel RAM with 8M pages Christophe Leroy
2016-02-09 16:07 ` [PATCH v8 03/23] powerpc: Update documentation for noltlbs kernel parameter Christophe Leroy
2016-02-09 16:07 ` [PATCH v8 04/23] powerpc/8xx: move setup_initial_memory_limit() into 8xx_mmu.c Christophe Leroy
2016-02-09 16:07 ` [PATCH v8 05/23] powerpc32: Fix pte_offset_kernel() to return NULL for bad pages Christophe Leroy
2016-02-09 16:07 ` [PATCH v8 06/23] powerpc32: refactor x_mapped_by_bats() and x_mapped_by_tlbcam() together Christophe Leroy
2016-02-09 16:08 ` [PATCH v8 07/23] powerpc/8xx: Fix vaddr for IMMR early remap Christophe Leroy
2016-03-11 22:51 ` [v8,07/23] " Scott Wood
2016-02-09 16:08 ` [PATCH v8 08/23] powerpc/8xx: Map IMMR area with 512k page at a fixed address Christophe Leroy
2016-03-11 23:15 ` Scott Wood [this message]
2016-03-12 9:55 ` [v8, " christophe leroy
2016-02-09 16:08 ` [PATCH v8 09/23] powerpc/8xx: CONFIG_PIN_TLB unneeded for CONFIG_PPC_EARLY_DEBUG_CPM Christophe Leroy
2016-02-09 16:08 ` [PATCH v8 10/23] powerpc/8xx: map more RAM at startup when needed Christophe Leroy
2016-02-09 16:08 ` [PATCH v8 11/23] powerpc32: Remove useless/wrong MMU:setio progress message Christophe Leroy
2016-02-09 16:08 ` [PATCH v8 12/23] powerpc32: remove ioremap_base Christophe Leroy
2016-02-09 16:08 ` [PATCH v8 13/23] powerpc/8xx: Add missing SPRN defines into reg_8xx.h Christophe Leroy
2016-02-09 16:08 ` [PATCH v8 14/23] powerpc/8xx: Handle CPU6 ERRATA directly in mtspr() macro Christophe Leroy
2016-02-09 16:08 ` [PATCH v8 15/23] powerpc/8xx: remove special handling of CPU6 errata in set_dec() Christophe Leroy
2016-02-09 16:08 ` [PATCH v8 16/23] powerpc/8xx: rewrite set_context() in C Christophe Leroy
2016-02-09 16:08 ` [PATCH v8 17/23] powerpc/8xx: rewrite flush_instruction_cache() " Christophe Leroy
2016-02-09 16:08 ` [PATCH v8 18/23] powerpc: add inline functions for cache related instructions Christophe Leroy
2016-02-09 16:08 ` [PATCH v8 19/23] powerpc32: Remove clear_pages() and define clear_page() inline Christophe Leroy
2016-02-09 16:08 ` [PATCH v8 20/23] powerpc32: move xxxxx_dcache_range() functions inline Christophe Leroy
2016-02-09 16:08 ` [PATCH v8 21/23] powerpc: Simplify test in __dma_sync() Christophe Leroy
2016-02-09 16:08 ` [PATCH v8 22/23] powerpc32: small optimisation in flush_icache_range() Christophe Leroy
2016-02-09 16:08 ` [PATCH v8 23/23] powerpc32: Remove one insn in mulhdu Christophe Leroy
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