From: Scott Wood <oss@buserror.net>
To: Zhao Qiang <qiang.zhao@nxp.com>
Cc: robh+dt@kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, xiaobo.xie@nxp.com,
leoyang.li@nxp.com, linuxppc-dev@lists.ozlabs.org
Subject: Re: [v5,1/7] QE: Add IC, SI and SIRAM document to device tree bindings.
Date: Mon, 16 May 2016 18:22:10 -0500 [thread overview]
Message-ID: <20160516232210.GA21087@home.buserror.net> (raw)
In-Reply-To: <1457486494-11377-1-git-send-email-qiang.zhao@nxp.com>
On Wed, Mar 09, 2016 at 09:21:28AM +0800, Zhao Qiang wrote:
> Add IC, SI and SIRAM document of QE to
> Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt
>
> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
> changes for v2
> - Add interrupt-controller in Required properties
> - delete address-cells and size-cells for qe-si and qe-siram
> Changes for v3
> - Add SoC specific caompatible strings to qe-si and qe-siram
> Changes for v4
> - NA
> Changes for v5
> - NA
>
> .../devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt | 50 ++++++++++++++++++++++
> 1 file changed, 50 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt
> index 4f89302..7ab21cb 100644
> --- a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt
> +++ b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt
> @@ -69,6 +69,56 @@ Example:
> };
> };
>
> +* Interrupt Controller (IC)
> +
> +Required properties:
> +- compatible : should be "fsl,qe-ic".
> +- reg : Address range of IC register set.
> +- interrupts : interrupts generated by the device.
> +- interrupt-controller : this device is a interrupt controller.
> +
> +Example:
> +
> + qeic: interrupt-controller@80 {
> + interrupt-controller;
> + compatible = "fsl,qe-ic";
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + reg = <0x80 0x80>;
> + interrupts = <95 2 0 0 94 2 0 0>; //high:79 low:78
> + };
Why is the information about which interrupt is "high" and which is
"low" in a comment in the example, rather than in the definition of the
interrupts property?
> +* Serial Interface Block (SI)
> +
> +The SI manages the routing of eight TDM lines to the QE block serial drivers
> +, the MCC and the UCCs, for receive and transmit.
> +
> +Required properties:
> +- compatible : should be "fsl,t1040-qe-si".
> +- reg : Address range of SI register set.
Is t1040 the only chip that has or will ever have this?
-Scott
next prev parent reply other threads:[~2016-05-16 23:22 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-09 1:21 [PATCH v5 1/7] QE: Add IC, SI and SIRAM document to device tree bindings Zhao Qiang
2016-03-09 1:21 ` [PATCH v5 2/7] QE: Add ucc hdlc document to bindings Zhao Qiang
2016-03-09 1:21 ` [PATCH v5 3/7] QE: Add uqe_serial " Zhao Qiang
2016-03-17 16:27 ` Rob Herring
2016-03-18 0:48 ` Qiang Zhao
2016-03-09 1:21 ` [PATCH v5 4/7] bindings: move cpm_qe binding from powerpc/fsl to soc/fsl Zhao Qiang
2016-03-09 1:21 ` [PATCH v5 5/7] T104xD4RDB: Add qe node to t104xd4rdb Zhao Qiang
2016-03-09 1:21 ` [PATCH v5 6/7] T104xRDB: Add qe node to t104xrdb Zhao Qiang
2016-03-09 1:21 ` [PATCH v5 7/7] T104xQDS: Add qe node to t104xqds Zhao Qiang
2016-05-16 23:22 ` Scott Wood [this message]
2016-05-17 1:18 ` [v5,1/7] QE: Add IC, SI and SIRAM document to device tree bindings Qiang Zhao
2016-05-17 1:41 ` Scott Wood
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