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From: Paul Mackerras <paulus@ozlabs.org>
To: Nicholas Piggin <npiggin@gmail.com>
Cc: linuxppc-dev@lists.ozlabs.org, kvm-ppc@vger.kernel.org
Subject: Re: [PATCH v2 12/14] KVM: PPC: Book3S HV: POWER9 can execute stop without a sync sequence
Date: Thu, 24 Aug 2017 20:27:35 +1000	[thread overview]
Message-ID: <20170824102735.GI27401@fergus.ozlabs.ibm.com> (raw)
In-Reply-To: <20170811163912.28783-13-npiggin@gmail.com>

On Sat, Aug 12, 2017 at 02:39:10AM +1000, Nicholas Piggin wrote:
> Reviewed-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---
>  arch/powerpc/kvm/book3s_hv_rmhandlers.S | 24 ++++++++++++------------
>  1 file changed, 12 insertions(+), 12 deletions(-)
> 
> diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
> index 3e024fd71fe8..edb47738a686 100644
> --- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S
> +++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
> @@ -2527,7 +2527,17 @@ BEGIN_FTR_SECTION
>  END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
>  
>  kvm_nap_sequence:		/* desired LPCR value in r5 */
> -BEGIN_FTR_SECTION
> +BEGIN_FTR_SECTION	/* nap sequence */
> +	mtspr	SPRN_LPCR,r5
> +	isync
> +	li	r0, 0
> +	std	r0, HSTATE_SCRATCH0(r13)
> +	ptesync
> +	ld	r0, HSTATE_SCRATCH0(r13)
> +1:	cmpd	r0, r0
> +	bne	1b
> +	nap
> +FTR_SECTION_ELSE	/* stop sequence */
>  	/*
>  	 * PSSCR bits:	exit criterion = 1 (wakeup based on LPCR at sreset)
>  	 *		enable state loss = 1 (allow SMT mode switch)
> @@ -2539,18 +2549,8 @@ BEGIN_FTR_SECTION
>  	li	r4, LPCR_PECE_HVEE@higher
>  	sldi	r4, r4, 32
>  	or	r5, r5, r4
> -END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
>  	mtspr	SPRN_LPCR,r5
> -	isync
> -	li	r0, 0
> -	std	r0, HSTATE_SCRATCH0(r13)
> -	ptesync
> -	ld	r0, HSTATE_SCRATCH0(r13)
> -1:	cmpd	r0, r0
> -	bne	1b
> -BEGIN_FTR_SECTION
> -	nap
> -FTR_SECTION_ELSE
> +
>  	PPC_STOP
>  ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
>  	b	.
> -- 
> 2.13.3

Currently we never get to kvm_nap_sequence on POWER9 because we are
always running one vcpu per vcore, so I haven't worried about this
code too much.  In future we might need this for running HPT guests on
a radix host, though.

Paul.

  reply	other threads:[~2017-08-24 10:27 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-08-11 16:38 [PATCH v2 00/14] idle and soft-irq improvements and POWER9 idle optimisation Nicholas Piggin
2017-08-11 16:38 ` [PATCH v2 01/14] powerpc/64s: masked interrupt avoid branch Nicholas Piggin
2017-08-24 12:37   ` [v2,01/14] " Michael Ellerman
2017-08-11 16:39 ` [PATCH v2 02/14] powerpc/64s: masked interrupt avoid instruction Nicholas Piggin
2017-08-11 16:39 ` [PATCH v2 03/14] powerpc/64s: masked interrupt returns to kernel so avoid r13 restore Nicholas Piggin
2017-08-11 16:39 ` [PATCH v2 04/14] powerpc/64: cleanup __check_irq_replay Nicholas Piggin
2017-08-11 16:39 ` [PATCH v2 05/14] powerpc/64s: irq replay merge HV and non-HV paths for doorbell replay Nicholas Piggin
2017-08-11 16:39 ` [PATCH v2 06/14] powerpc/64s: irq replay external use the HV handler in HV mode on POWER9 Nicholas Piggin
2017-08-11 16:39 ` [PATCH v2 07/14] powerpc/64: remove redundant instruction in interrupt replay Nicholas Piggin
2017-08-11 16:39 ` [PATCH v2 08/14] powerpc/64s: irq replay remove spurious irq reason Nicholas Piggin
2017-08-11 16:39 ` [PATCH v2 09/14] powerpc/64: runlatch CTRL[RUN] set optimisation Nicholas Piggin
2017-08-11 16:39 ` [PATCH v2 10/14] KVM: PPC: Book3S HV: POWER9 does not require secondary thread management Nicholas Piggin
2017-08-24  9:34   ` Paul Mackerras
2017-08-24 12:45     ` Nicholas Piggin
2017-08-11 16:39 ` [PATCH v2 11/14] powerpc/64s: idle POWER9 can execute stop without a sync sequence Nicholas Piggin
2017-08-11 16:39 ` [PATCH v2 12/14] KVM: PPC: Book3S HV: " Nicholas Piggin
2017-08-24 10:27   ` Paul Mackerras [this message]
2017-08-24 12:53     ` Nicholas Piggin
2017-08-11 16:39 ` [PATCH v2 13/14] powerpc/64s: idle POWER9 can execute stop in virtual mode Nicholas Piggin
2017-08-11 16:39 ` [PATCH v2 14/14] powerpc/64s: idle ESL=0 stop can avoid MSR and save/restore overhead Nicholas Piggin

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