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From: Bao Xiaowei <xiaowei.bao@nxp.com>
To: <robh+dt@kernel.org>, <mark.rutland@arm.com>,
	<catalin.marinas@arm.com>, <will.deacon@arm.com>,
	<bhelgaas@google.com>, <shawnguo@kernel.org>,
	<madalin.bucur@nxp.com>, <sumit.garg@nxp.com>,
	<yangbo.lu@nxp.com>, <hongtao.jia@nxp.com>,
	<Yuantian.Tang@nxp.com>, <leoyang.li@nxp.com>, <kishon@ti.com>,
	<jingoohan1@gmail.com>, <pbrobinson@gmail.com>,
	<songxiaowei@hisilicon.com>, <devicetree@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <linux-pci@vger.kernel.org>,
	<linuxppc-dev@lists.ozlabs.org>, <Zhiqiang.Hou@nxp.com>,
	<mingkai.hu@nxp.com>, <Minghuan.Lian@nxp.com>
Cc: Bao Xiaowei <xiaowei.bao@nxp.com>
Subject: [PATCHv3 1/3] ARMv8: dts: ls1046a: add the property of IB and OB
Date: Fri, 10 Nov 2017 10:49:24 +0800	[thread overview]
Message-ID: <20171110024926.39700-2-xiaowei.bao@nxp.com> (raw)
In-Reply-To: <20171110024926.39700-1-xiaowei.bao@nxp.com>

Add the property of inbound and outbound windows number for ep
driver.

Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
Acked-by: Minghuan Lian <minghuan.Lian@nxp.com>
---
 v2:
 - no change
 v3:
 - modify the commit message

 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 06b5e12d04d8..f8332669663c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -674,6 +674,8 @@
 			device_type = "pci";
 			dma-coherent;
 			num-lanes = <4>;
+			num-ib-windows = <6>;
+			num-ob-windows = <6>;
 			bus-range = <0x0 0xff>;
 			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
 				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
@@ -699,6 +701,8 @@
 			device_type = "pci";
 			dma-coherent;
 			num-lanes = <2>;
+			num-ib-windows = <6>;
+			num-ob-windows = <6>;
 			bus-range = <0x0 0xff>;
 			ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
 				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
@@ -724,6 +728,8 @@
 			device_type = "pci";
 			dma-coherent;
 			num-lanes = <2>;
+			num-ib-windows = <6>;
+			num-ob-windows = <6>;
 			bus-range = <0x0 0xff>;
 			ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */
 				  0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
-- 
2.14.1

  reply	other threads:[~2017-11-10  3:08 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-11-10  2:49 [PATCHv3 0/3] dts: Add the property of IB and OB Bao Xiaowei
2017-11-10  2:49 ` Bao Xiaowei [this message]
2017-11-10  2:49 ` [PATCHv3 2/3] ARMv8: layerscape: add the pcie ep function support Bao Xiaowei
2017-11-10  3:30   ` M.h. Lian
2017-11-10  2:49 ` [PATCHv3 3/3] ARMv8: pcie: make the DWC EP driver support for layerscape Bao Xiaowei

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