From: Nicholas Piggin <npiggin@gmail.com>
To: "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com>
Cc: benh@kernel.crashing.org, paulus@samba.org, mpe@ellerman.id.au,
linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH 2/2] powerpc/mm/radix: Change pte relax sequence to handle nest MMU hang
Date: Mon, 28 May 2018 18:59:26 +1000 [thread overview]
Message-ID: <20180528185926.64e4288b@roar.ozlabs.ibm.com> (raw)
In-Reply-To: <20180525154917.23163-2-aneesh.kumar@linux.ibm.com>
On Fri, 25 May 2018 21:19:17 +0530
"Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com> wrote:
> When relaxing access (read -> read_write update), pte need to be marked invalid
> to handle a nest MMU bug. We also need to do a tlb flush after the pte is
> marked invalid before updating the pte with new access bits.
>
> We also move tlb flush to platform specific __ptep_set_access_flags. This will
> help us to gerid of unnecessary tlb flush on BOOK3S 64 later. We don't do that
> in this patch. This also helps in avoiding multiple tlbies with coprocessor
> attached.
>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
I think these look good to me, but same comment: can you split the API
change from the NMMU fix? The fix is just a couple of lines, and the
rest of the API change should leave generated code almost unchanged, so
it would be easier to review if these are split.
Thanks,
Nick
prev parent reply other threads:[~2018-05-28 8:59 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-25 15:49 [PATCH 1/2] powerpc/mm/radix: Move functions from radix.h to pgtable-radix.c Aneesh Kumar K.V
2018-05-25 15:49 ` [PATCH 2/2] powerpc/mm/radix: Change pte relax sequence to handle nest MMU hang Aneesh Kumar K.V
2018-05-28 8:59 ` Nicholas Piggin [this message]
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