On Tue, Nov 13, 2018 at 07:28:12PM +1100, Alexey Kardashevskiy wrote:
> We already changed NPU API for GPUs to not to call OPAL and the remaining
> bit is initializing NPU structures.
> 
> This uses a new QEMU capability which marks NPU-enabled vPHBs as
> "IBM,npu-vphb" and initializes an NPU structure per vPHB.
> 
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> ---
>  arch/powerpc/platforms/pseries/pci.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/arch/powerpc/platforms/pseries/pci.c b/arch/powerpc/platforms/pseries/pci.c
> index 41d8a4d..a50d5e4 100644
> --- a/arch/powerpc/platforms/pseries/pci.c
> +++ b/arch/powerpc/platforms/pseries/pci.c
> @@ -29,6 +29,7 @@
>  #include <asm/pci-bridge.h>
>  #include <asm/prom.h>
>  #include <asm/ppc-pci.h>
> +#include <asm/pci.h>
>  #include "pseries.h"
>  
>  #if 0
> @@ -237,6 +238,8 @@ static void __init pSeries_request_regions(void)
>  
>  void __init pSeries_final_fixup(void)
>  {
> +	struct pci_controller *hose;
> +
>  	pSeries_request_regions();
>  
>  	eeh_probe_devices();
> @@ -246,6 +249,9 @@ void __init pSeries_final_fixup(void)
>  	ppc_md.pcibios_sriov_enable = pseries_pcibios_sriov_enable;
>  	ppc_md.pcibios_sriov_disable = pseries_pcibios_sriov_disable;
>  #endif
> +	list_for_each_entry(hose, &hose_list, list_node)
> +		if (of_device_is_compatible(hose->dn, "IBM,npu-vphb"))
> +			pnv_npu2_init(hose);

I take it from this the NPUs are showing up with a compatible property
that lists the normal PHB value as well as IBM,npu-vphb.  Since AIUI
the NPUs act quite differently from other (real) PHBs this seems
bogus.  Shouldn't they be probed separately?

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
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