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dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: lists.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="Zj9aCeOl"; dkim-atps=neutral Received: by ozlabs.org (Postfix, from userid 1007) id 42x6Zy5xRlz9sBN; Fri, 16 Nov 2018 16:43:06 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1542346986; bh=tWqZPs6YvZL30UvfFfGoyqCrahNh+++52YVchTrThKE=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=Zj9aCeOl8eYcMJVkuKH9BlgKrZcisF/jL9mEYa7yxkL/CudOpA6KxO06wyR93C+Hs lmfiXuujXS8b/TtD9hT6wYUJxELxGtJfJH+KtwkNQZuJmywrdB5Fbv2vpZ5peW5n9l D+lbT5r62Wq/zjmu+w2awdNJ9gzin52Sq67K6ZWY= Date: Fri, 16 Nov 2018 16:25:34 +1100 From: David Gibson To: Alexey Kardashevskiy Subject: Re: [PATCH kernel v3 11/22] powerpc/pseries/npu: Enable platform support Message-ID: <20181116052534.GD23632@umbus> References: <20181113082823.2440-1-aik@ozlabs.ru> <20181113082823.2440-12-aik@ozlabs.ru> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="/unnNtmY43mpUSKx" Content-Disposition: inline In-Reply-To: <20181113082823.2440-12-aik@ozlabs.ru> User-Agent: Mutt/1.10.1 (2018-07-13) X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alex Williamson , Jose Ricardo Ziviani , Sam Bobroff , Alistair Popple , linuxppc-dev@lists.ozlabs.org, kvm-ppc@vger.kernel.org, Piotr Jaroszynski , Oliver O'Halloran , Andrew Donnellan , Leonardo Augusto =?iso-8859-1?Q?Guimar=E3es?= Garcia , Reza Arbab Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" --/unnNtmY43mpUSKx Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Nov 13, 2018 at 07:28:12PM +1100, Alexey Kardashevskiy wrote: > We already changed NPU API for GPUs to not to call OPAL and the remaining > bit is initializing NPU structures. >=20 > This uses a new QEMU capability which marks NPU-enabled vPHBs as > "IBM,npu-vphb" and initializes an NPU structure per vPHB. >=20 > Signed-off-by: Alexey Kardashevskiy > --- > arch/powerpc/platforms/pseries/pci.c | 6 ++++++ > 1 file changed, 6 insertions(+) >=20 > diff --git a/arch/powerpc/platforms/pseries/pci.c b/arch/powerpc/platform= s/pseries/pci.c > index 41d8a4d..a50d5e4 100644 > --- a/arch/powerpc/platforms/pseries/pci.c > +++ b/arch/powerpc/platforms/pseries/pci.c > @@ -29,6 +29,7 @@ > #include > #include > #include > +#include > #include "pseries.h" > =20 > #if 0 > @@ -237,6 +238,8 @@ static void __init pSeries_request_regions(void) > =20 > void __init pSeries_final_fixup(void) > { > + struct pci_controller *hose; > + > pSeries_request_regions(); > =20 > eeh_probe_devices(); > @@ -246,6 +249,9 @@ void __init pSeries_final_fixup(void) > ppc_md.pcibios_sriov_enable =3D pseries_pcibios_sriov_enable; > ppc_md.pcibios_sriov_disable =3D pseries_pcibios_sriov_disable; > #endif > + list_for_each_entry(hose, &hose_list, list_node) > + if (of_device_is_compatible(hose->dn, "IBM,npu-vphb")) > + pnv_npu2_init(hose); I take it from this the NPUs are showing up with a compatible property that lists the normal PHB value as well as IBM,npu-vphb. Since AIUI the NPUs act quite differently from other (real) PHBs this seems bogus. Shouldn't they be probed separately? --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. 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