* [PATCHv4 1/2] PCI: layerscape: Add the bar_fixed_64bit property in EP driver.
@ 2019-08-13 2:53 Xiaowei Bao
2019-08-13 2:53 ` [PATCHv4 2/2] PCI: layerscape: Add CONFIG_PCI_LAYERSCAPE_EP to build EP/RC separately Xiaowei Bao
2019-08-13 4:36 ` [PATCHv4 1/2] PCI: layerscape: Add the bar_fixed_64bit property in EP driver Kishon Vijay Abraham I
0 siblings, 2 replies; 4+ messages in thread
From: Xiaowei Bao @ 2019-08-13 2:53 UTC (permalink / raw)
To: lorenzo.pieralisi, bhelgaas, minghuan.Lian, mingkai.hu, roy.zang,
l.stach, kishon, tpiepho, leonard.crestez, andrew.smirnov,
yue.wang, hayashi.kunihiko, dwmw, jonnyc, linux-pci,
linux-kernel, linuxppc-dev, linux-arm-kernel
Cc: Xiaowei Bao
The PCIe controller of layerscape just have 4 BARs, BAR0 and BAR1
is 32bit, BAR3 and BAR4 is 64bit, this is determined by hardware,
so set the bar_fixed_64bit with 0x14.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
---
v2:
- Replace value 0x14 with a macro.
v3:
- No change.
v4:
- send the patch again with '--to'.
drivers/pci/controller/dwc/pci-layerscape-ep.c | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c
index be61d96..227c33b 100644
--- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
+++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
@@ -44,6 +44,7 @@ static int ls_pcie_establish_link(struct dw_pcie *pci)
.linkup_notifier = false,
.msi_capable = true,
.msix_capable = false,
+ .bar_fixed_64bit = (1 << BAR_2) | (1 << BAR_4),
};
static const struct pci_epc_features*
--
1.7.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCHv4 2/2] PCI: layerscape: Add CONFIG_PCI_LAYERSCAPE_EP to build EP/RC separately
2019-08-13 2:53 [PATCHv4 1/2] PCI: layerscape: Add the bar_fixed_64bit property in EP driver Xiaowei Bao
@ 2019-08-13 2:53 ` Xiaowei Bao
2019-08-13 4:36 ` [PATCHv4 1/2] PCI: layerscape: Add the bar_fixed_64bit property in EP driver Kishon Vijay Abraham I
1 sibling, 0 replies; 4+ messages in thread
From: Xiaowei Bao @ 2019-08-13 2:53 UTC (permalink / raw)
To: lorenzo.pieralisi, bhelgaas, minghuan.Lian, mingkai.hu, roy.zang,
l.stach, kishon, tpiepho, leonard.crestez, andrew.smirnov,
yue.wang, hayashi.kunihiko, dwmw, jonnyc, linux-pci,
linux-kernel, linuxppc-dev, linux-arm-kernel
Cc: Xiaowei Bao
Add CONFIG_PCI_LAYERSCAPE_EP to build EP/RC separately.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
---
v2:
- No change.
v3:
- modify the commit message.
v4:
- send the patch again with '--to'.
drivers/pci/controller/dwc/Kconfig | 20 ++++++++++++++++++--
drivers/pci/controller/dwc/Makefile | 3 ++-
2 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
index a6ce1ee..a41ccf5 100644
--- a/drivers/pci/controller/dwc/Kconfig
+++ b/drivers/pci/controller/dwc/Kconfig
@@ -131,13 +131,29 @@ config PCI_KEYSTONE_EP
DesignWare core functions to implement the driver.
config PCI_LAYERSCAPE
- bool "Freescale Layerscape PCIe controller"
+ bool "Freescale Layerscape PCIe controller - Host mode"
depends on OF && (ARM || ARCH_LAYERSCAPE || COMPILE_TEST)
depends on PCI_MSI_IRQ_DOMAIN
select MFD_SYSCON
select PCIE_DW_HOST
help
- Say Y here if you want PCIe controller support on Layerscape SoCs.
+ Say Y here if you want to enable PCIe controller support on Layerscape
+ SoCs to work in Host mode.
+ This controller can work either as EP or RC. The RCW[HOST_AGT_PEX]
+ determines which PCIe controller works in EP mode and which PCIe
+ controller works in RC mode.
+
+config PCI_LAYERSCAPE_EP
+ bool "Freescale Layerscape PCIe controller - Endpoint mode"
+ depends on OF && (ARM || ARCH_LAYERSCAPE || COMPILE_TEST)
+ depends on PCI_ENDPOINT
+ select PCIE_DW_EP
+ help
+ Say Y here if you want to enable PCIe controller support on Layerscape
+ SoCs to work in Endpoint mode.
+ This controller can work either as EP or RC. The RCW[HOST_AGT_PEX]
+ determines which PCIe controller works in EP mode and which PCIe
+ controller works in RC mode.
config PCI_HISI
depends on OF && (ARM64 || COMPILE_TEST)
diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
index b085dfd..824fde7 100644
--- a/drivers/pci/controller/dwc/Makefile
+++ b/drivers/pci/controller/dwc/Makefile
@@ -8,7 +8,8 @@ obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone.o
-obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o pci-layerscape-ep.o
+obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
+obj-$(CONFIG_PCI_LAYERSCAPE_EP) += pci-layerscape-ep.o
obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
--
1.7.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCHv4 1/2] PCI: layerscape: Add the bar_fixed_64bit property in EP driver.
2019-08-13 2:53 [PATCHv4 1/2] PCI: layerscape: Add the bar_fixed_64bit property in EP driver Xiaowei Bao
2019-08-13 2:53 ` [PATCHv4 2/2] PCI: layerscape: Add CONFIG_PCI_LAYERSCAPE_EP to build EP/RC separately Xiaowei Bao
@ 2019-08-13 4:36 ` Kishon Vijay Abraham I
2019-08-13 6:29 ` [EXT] " Xiaowei Bao
1 sibling, 1 reply; 4+ messages in thread
From: Kishon Vijay Abraham I @ 2019-08-13 4:36 UTC (permalink / raw)
To: Xiaowei Bao, lorenzo.pieralisi, bhelgaas, minghuan.Lian,
mingkai.hu, roy.zang, l.stach, tpiepho, leonard.crestez,
andrew.smirnov, yue.wang, hayashi.kunihiko, dwmw, jonnyc,
linux-pci, linux-kernel, linuxppc-dev, linux-arm-kernel
On 13/08/19 8:23 AM, Xiaowei Bao wrote:
> The PCIe controller of layerscape just have 4 BARs, BAR0 and BAR1
> is 32bit, BAR3 and BAR4 is 64bit, this is determined by hardware,
Do you mean BAR2 instead of BAR3 here?
Thanks
Kishon
> so set the bar_fixed_64bit with 0x14.
>
> Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> ---
> v2:
> - Replace value 0x14 with a macro.
> v3:
> - No change.
> v4:
> - send the patch again with '--to'.
>
> drivers/pci/controller/dwc/pci-layerscape-ep.c | 1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> index be61d96..227c33b 100644
> --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
> +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> @@ -44,6 +44,7 @@ static int ls_pcie_establish_link(struct dw_pcie *pci)
> .linkup_notifier = false,
> .msi_capable = true,
> .msix_capable = false,
> + .bar_fixed_64bit = (1 << BAR_2) | (1 << BAR_4),
> };
>
> static const struct pci_epc_features*
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* RE: [EXT] Re: [PATCHv4 1/2] PCI: layerscape: Add the bar_fixed_64bit property in EP driver.
2019-08-13 4:36 ` [PATCHv4 1/2] PCI: layerscape: Add the bar_fixed_64bit property in EP driver Kishon Vijay Abraham I
@ 2019-08-13 6:29 ` Xiaowei Bao
0 siblings, 0 replies; 4+ messages in thread
From: Xiaowei Bao @ 2019-08-13 6:29 UTC (permalink / raw)
To: Kishon Vijay Abraham I, lorenzo.pieralisi, bhelgaas, M.h. Lian,
Mingkai Hu, Roy Zang, l.stach, tpiepho, Leonard Crestez,
andrew.smirnov, yue.wang, hayashi.kunihiko, dwmw, jonnyc,
linux-pci, linux-kernel, linuxppc-dev, linux-arm-kernel
> -----Original Message-----
> From: Kishon Vijay Abraham I <kishon@ti.com>
> Sent: 2019年8月13日 12:36
> To: Xiaowei Bao <xiaowei.bao@nxp.com>; lorenzo.pieralisi@arm.com;
> bhelgaas@google.com; M.h. Lian <minghuan.lian@nxp.com>; Mingkai Hu
> <mingkai.hu@nxp.com>; Roy Zang <roy.zang@nxp.com>;
> l.stach@pengutronix.de; tpiepho@impinj.com; Leonard Crestez
> <leonard.crestez@nxp.com>; andrew.smirnov@gmail.com;
> yue.wang@amlogic.com; hayashi.kunihiko@socionext.com;
> dwmw@amazon.co.uk; jonnyc@amazon.com; linux-pci@vger.kernel.org;
> linux-kernel@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> linux-arm-kernel@lists.infradead.org
> Subject: [EXT] Re: [PATCHv4 1/2] PCI: layerscape: Add the bar_fixed_64bit
> property in EP driver.
>
> Caution: EXT Email
>
> On 13/08/19 8:23 AM, Xiaowei Bao wrote:
> > The PCIe controller of layerscape just have 4 BARs, BAR0 and BAR1 is
> > 32bit, BAR3 and BAR4 is 64bit, this is determined by hardware,
>
> Do you mean BAR2 instead of BAR3 here?
Yes.
>
> Thanks
> Kishon
>
> > so set the bar_fixed_64bit with 0x14.
> >
> > Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> > ---
> > v2:
> > - Replace value 0x14 with a macro.
> > v3:
> > - No change.
> > v4:
> > - send the patch again with '--to'.
> >
> > drivers/pci/controller/dwc/pci-layerscape-ep.c | 1 +
> > 1 files changed, 1 insertions(+), 0 deletions(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > index be61d96..227c33b 100644
> > --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > @@ -44,6 +44,7 @@ static int ls_pcie_establish_link(struct dw_pcie *pci)
> > .linkup_notifier = false,
> > .msi_capable = true,
> > .msix_capable = false,
> > + .bar_fixed_64bit = (1 << BAR_2) | (1 << BAR_4),
> > };
> >
> > static const struct pci_epc_features*
> >
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2019-08-13 6:31 UTC | newest]
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2019-08-13 2:53 [PATCHv4 1/2] PCI: layerscape: Add the bar_fixed_64bit property in EP driver Xiaowei Bao
2019-08-13 2:53 ` [PATCHv4 2/2] PCI: layerscape: Add CONFIG_PCI_LAYERSCAPE_EP to build EP/RC separately Xiaowei Bao
2019-08-13 4:36 ` [PATCHv4 1/2] PCI: layerscape: Add the bar_fixed_64bit property in EP driver Kishon Vijay Abraham I
2019-08-13 6:29 ` [EXT] " Xiaowei Bao
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