From: "Alastair D'Silva" <alastair@au1.ibm.com>
To: alastair@d-silva.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
David Hildenbrand <david@redhat.com>,
linux-kernel@vger.kernel.org, stable@vger.kernel.org,
Mike Rapoport <rppt@linux.vnet.ibm.com>,
Paul Mackerras <paulus@samba.org>,
Nicholas Piggin <npiggin@gmail.com>, Qian Cai <cai@lca.pw>,
Thomas Gleixner <tglx@linutronix.de>,
linuxppc-dev@lists.ozlabs.org,
Andrew Morton <akpm@linux-foundation.org>,
Allison Randal <allison@lohutok.net>
Subject: [PATCH 1/6] powerpc: Allow flush_icache_range to work across ranges >4GB
Date: Thu, 15 Aug 2019 14:10:46 +1000 [thread overview]
Message-ID: <20190815041057.13627-2-alastair@au1.ibm.com> (raw)
In-Reply-To: <20190815041057.13627-1-alastair@au1.ibm.com>
From: Alastair D'Silva <alastair@d-silva.org>
When calling flush_icache_range with a size >4GB, we were masking
off the upper 32 bits, so we would incorrectly flush a range smaller
than intended.
This patch replaces the 32 bit shifts with 64 bit ones, so that
the full size is accounted for.
Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
Cc: stable@vger.kernel.org
---
arch/powerpc/kernel/misc_64.S | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S
index b55a7b4cb543..9bc0aa9aeb65 100644
--- a/arch/powerpc/kernel/misc_64.S
+++ b/arch/powerpc/kernel/misc_64.S
@@ -82,7 +82,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
subf r8,r6,r4 /* compute length */
add r8,r8,r5 /* ensure we get enough */
lwz r9,DCACHEL1LOGBLOCKSIZE(r10) /* Get log-2 of cache block size */
- srw. r8,r8,r9 /* compute line count */
+ srd. r8,r8,r9 /* compute line count */
beqlr /* nothing to do? */
mtctr r8
1: dcbst 0,r6
@@ -98,7 +98,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
subf r8,r6,r4 /* compute length */
add r8,r8,r5
lwz r9,ICACHEL1LOGBLOCKSIZE(r10) /* Get log-2 of Icache block size */
- srw. r8,r8,r9 /* compute line count */
+ srd. r8,r8,r9 /* compute line count */
beqlr /* nothing to do? */
mtctr r8
2: icbi 0,r6
--
2.21.0
next prev parent reply other threads:[~2019-08-15 4:14 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-15 4:10 [PATCH 0/6] powerpc: convert cache asm to C Alastair D'Silva
2019-08-15 4:10 ` Alastair D'Silva [this message]
2019-08-15 4:10 ` [PATCH 2/6] powerpc: define helpers to get L1 icache sizes Alastair D'Silva
2019-08-15 4:10 ` [PATCH 3/6] powerpc: Convert flush_icache_range & friends to C Alastair D'Silva
2019-08-15 7:29 ` christophe leroy
2019-08-16 1:44 ` Alastair D'Silva
2019-08-16 15:57 ` Christophe Leroy
2019-08-15 4:10 ` [PATCH 4/6] powerpc: Chunk calls to flush_dcache_range in arch_*_memory Alastair D'Silva
2019-08-15 6:54 ` Mike Rapoport
2019-08-15 7:36 ` christophe leroy
2019-08-16 1:45 ` Alastair D'Silva
2019-08-15 4:10 ` [PATCH 5/6] powerpc: Remove 'extern' from func prototypes in cache headers Alastair D'Silva
2019-08-15 4:10 ` [PATCH 6/6] powerpc: Don't flush caches when adding memory Alastair D'Silva
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