From: Peter Zijlstra <peterz@infradead.org>
To: Ravi Bangoria <ravi.bangoria@linux.ibm.com>
Cc: mark.rutland@arm.com, ak@linux.intel.com, maddy@linux.ibm.com,
alexander.shishkin@linux.intel.com, jolsa@redhat.com,
linux-kernel@vger.kernel.org, eranian@google.com,
adrian.hunter@intel.com, robert.richter@amd.com,
yao.jin@linux.intel.com, mingo@redhat.com, paulus@samba.org,
acme@kernel.org, namhyung@kernel.org, kim.phillips@amd.com,
linuxppc-dev@lists.ozlabs.org, alexey.budankov@linux.intel.com,
kan.liang@linux.intel.com
Subject: Re: [RFC 00/11] perf: Enhancing perf to export processor hazard information
Date: Mon, 2 Mar 2020 11:13:32 +0100 [thread overview]
Message-ID: <20200302101332.GS18400@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <20200302052355.36365-1-ravi.bangoria@linux.ibm.com>
On Mon, Mar 02, 2020 at 10:53:44AM +0530, Ravi Bangoria wrote:
> Modern processors export such hazard data in Performance
> Monitoring Unit (PMU) registers. Ex, 'Sampled Instruction Event
> Register' on IBM PowerPC[1][2] and 'Instruction-Based Sampling' on
> AMD[3] provides similar information.
>
> Implementation detail:
>
> A new sample_type called PERF_SAMPLE_PIPELINE_HAZ is introduced.
> If it's set, kernel converts arch specific hazard information
> into generic format:
>
> struct perf_pipeline_haz_data {
> /* Instruction/Opcode type: Load, Store, Branch .... */
> __u8 itype;
> /* Instruction Cache source */
> __u8 icache;
> /* Instruction suffered hazard in pipeline stage */
> __u8 hazard_stage;
> /* Hazard reason */
> __u8 hazard_reason;
> /* Instruction suffered stall in pipeline stage */
> __u8 stall_stage;
> /* Stall reason */
> __u8 stall_reason;
> __u16 pad;
> };
Kim, does this format indeed work for AMD IBS?
next prev parent reply other threads:[~2020-03-02 10:15 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-02 5:23 [RFC 00/11] perf: Enhancing perf to export processor hazard information Ravi Bangoria
2020-03-02 5:23 ` [RFC 01/11] powerpc/perf: Simplify ISA207_SIER macros Ravi Bangoria
2020-03-02 5:23 ` [RFC 02/11] perf/core: Data structure to present hazard data Ravi Bangoria
2020-03-02 9:55 ` Peter Zijlstra
2020-03-02 14:23 ` maddy
2020-03-02 14:48 ` Mark Rutland
2020-03-03 14:32 ` Ravi Bangoria
2020-03-02 14:54 ` Mark Rutland
2020-03-03 14:31 ` Ravi Bangoria
2020-03-02 5:23 ` [RFC 03/11] powerpc/perf: Arch specific definitions for pipeline Ravi Bangoria
2020-03-02 5:23 ` [RFC 04/11] powerpc/perf: Arch support to expose Hazard data Ravi Bangoria
2020-03-02 5:23 ` [RFC 05/11] perf tools: Enable record and script to record and show hazard data Ravi Bangoria
2020-03-02 5:23 ` [RFC 06/11] perf hists: Make a room for hazard info in struct hist_entry Ravi Bangoria
2020-03-02 5:23 ` [RFC 07/11] perf hazard: Functions to convert generic hazard data to arch specific string Ravi Bangoria
2020-03-02 5:23 ` [RFC 08/11] perf report: Enable hazard mode Ravi Bangoria
2020-03-02 5:23 ` [RFC 09/11] perf annotate: Introduce type for annotation_line Ravi Bangoria
2020-03-02 5:23 ` [RFC 10/11] perf annotate: Preparation for hazard Ravi Bangoria
2020-03-02 5:23 ` [RFC 11/11] perf annotate: Show hazard data in tui mode Ravi Bangoria
2020-03-02 10:13 ` Peter Zijlstra [this message]
2020-03-02 20:21 ` [RFC 00/11] perf: Enhancing perf to export processor hazard information Stephane Eranian
2020-03-02 22:25 ` Kim Phillips
2020-03-05 4:46 ` Ravi Bangoria
2020-03-05 22:06 ` Kim Phillips
2020-03-11 16:00 ` Ravi Bangoria
2020-03-12 22:38 ` Kim Phillips
2020-03-17 6:50 ` maddy
2020-03-18 17:35 ` Kim Phillips
2020-03-19 11:22 ` Michael Ellerman
2020-03-26 10:19 ` maddy
2020-03-26 19:48 ` Kim Phillips
2020-04-20 7:09 ` Madhavan Srinivasan
2020-04-27 7:18 ` Madhavan Srinivasan
2020-03-05 4:28 ` maddy
2020-03-03 1:33 ` Andi Kleen
2020-03-05 5:06 ` Ravi Bangoria
2020-03-02 21:08 ` Paul Clarke
2020-03-05 5:06 ` Ravi Bangoria
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