From: Jordan Niethe <jniethe5@gmail.com>
To: linuxppc-dev@lists.ozlabs.org
Cc: alistair@popple.id.au, npiggin@gmail.com, bala24@linux.ibm.com,
naveen.n.rao@linux.vnet.ibm.com,
Jordan Niethe <jniethe5@gmail.com>,
dja@axtens.net
Subject: [PATCH v8 21/30] powerpc: Enable Prefixed Instructions
Date: Wed, 6 May 2020 13:40:41 +1000 [thread overview]
Message-ID: <20200506034050.24806-22-jniethe5@gmail.com> (raw)
In-Reply-To: <20200506034050.24806-1-jniethe5@gmail.com>
From: Alistair Popple <alistair@popple.id.au>
Prefix instructions have their own FSCR bit which needs to enabled via
a CPU feature. The kernel will save the FSCR for problem state but it
needs to be enabled initially.
If prefixed instructions are made unavailable by the [H]FSCR, attempting
to use them will cause a facility unavailable exception. Add "PREFIX" to
the facility_strings[].
Currently there are no prefixed instructions that are actually emulated
by emulate_instruction() within facility_unavailable_exception().
However, when caused by a prefixed instructions the SRR1 PREFIXED bit is
set. Prepare for dealing with emulated prefixed instructions by checking
for this bit.
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Jordan Niethe <jniethe5@gmail.com>
---
v4:
- Squash "Check for prefixed instructions in
facility_unavailable_exception()" here
- Remove dt parts for now
---
arch/powerpc/include/asm/reg.h | 3 +++
arch/powerpc/kernel/traps.c | 1 +
2 files changed, 4 insertions(+)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index da5cab038e25..773f76402392 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -397,6 +397,7 @@
#define SPRN_RWMR 0x375 /* Region-Weighting Mode Register */
/* HFSCR and FSCR bit numbers are the same */
+#define FSCR_PREFIX_LG 13 /* Enable Prefix Instructions */
#define FSCR_SCV_LG 12 /* Enable System Call Vectored */
#define FSCR_MSGP_LG 10 /* Enable MSGP */
#define FSCR_TAR_LG 8 /* Enable Target Address Register */
@@ -408,11 +409,13 @@
#define FSCR_VECVSX_LG 1 /* Enable VMX/VSX */
#define FSCR_FP_LG 0 /* Enable Floating Point */
#define SPRN_FSCR 0x099 /* Facility Status & Control Register */
+#define FSCR_PREFIX __MASK(FSCR_PREFIX_LG)
#define FSCR_SCV __MASK(FSCR_SCV_LG)
#define FSCR_TAR __MASK(FSCR_TAR_LG)
#define FSCR_EBB __MASK(FSCR_EBB_LG)
#define FSCR_DSCR __MASK(FSCR_DSCR_LG)
#define SPRN_HFSCR 0xbe /* HV=1 Facility Status & Control Register */
+#define HFSCR_PREFIX __MASK(FSCR_PREFIX_LG)
#define HFSCR_MSGP __MASK(FSCR_MSGP_LG)
#define HFSCR_TAR __MASK(FSCR_TAR_LG)
#define HFSCR_EBB __MASK(FSCR_EBB_LG)
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 3fca22276bb1..493a3fa0ac1a 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -1720,6 +1720,7 @@ void facility_unavailable_exception(struct pt_regs *regs)
[FSCR_TAR_LG] = "TAR",
[FSCR_MSGP_LG] = "MSGP",
[FSCR_SCV_LG] = "SCV",
+ [FSCR_PREFIX_LG] = "PREFIX",
};
char *facility = "unknown";
u64 value;
--
2.17.1
next prev parent reply other threads:[~2020-05-06 4:22 UTC|newest]
Thread overview: 80+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-06 3:40 [PATCH v8 00/30] Initial Prefixed Instruction support Jordan Niethe
2020-05-06 3:40 ` [PATCH v8 01/30] powerpc/xmon: Remove store_inst() for patch_instruction() Jordan Niethe
2020-05-06 3:40 ` [PATCH v8 02/30] powerpc/xmon: Move breakpoint instructions to own array Jordan Niethe
2020-05-06 3:40 ` [PATCH v8 03/30] powerpc/xmon: Move breakpoints to text section Jordan Niethe
2020-05-06 3:40 ` [PATCH v8 04/30] powerpc/xmon: Use bitwise calculations in_breakpoint_table() Jordan Niethe
2020-05-06 3:40 ` [PATCH v8 05/30] powerpc: Change calling convention for create_branch() et. al Jordan Niethe
2020-05-06 3:40 ` [PATCH v8 06/30] powerpc: Use a macro for creating instructions from u32s Jordan Niethe
2020-05-06 3:40 ` [PATCH v8 07/30] powerpc: Use an accessor for instructions Jordan Niethe
2020-05-06 3:40 ` [PATCH v8 08/30] powerpc: Use a function for getting the instruction op code Jordan Niethe
2020-05-15 7:48 ` Jordan Niethe
2020-05-16 11:08 ` Michael Ellerman
2020-05-17 7:41 ` Jordan Niethe
2020-05-06 3:40 ` [PATCH v8 09/30] powerpc: Use a function for byte swapping instructions Jordan Niethe
2020-05-06 3:40 ` [PATCH v8 10/30] powerpc: Introduce functions for instruction equality Jordan Niethe
2020-05-06 3:40 ` [PATCH v8 11/30] powerpc: Use a datatype for instructions Jordan Niethe
2020-05-08 1:51 ` Jordan Niethe
2020-05-08 7:17 ` Christophe Leroy
2020-05-11 1:19 ` Jordan Niethe
2020-05-08 2:15 ` Jordan Niethe
2020-05-17 10:48 ` Jordan Niethe
2020-05-06 3:40 ` [PATCH v8 12/30] powerpc: Use a function for reading instructions Jordan Niethe
2020-05-16 18:39 ` Christophe Leroy
2020-05-17 10:44 ` Jordan Niethe
2020-05-19 4:05 ` Michael Ellerman
2020-05-19 5:03 ` Christophe Leroy
2020-05-20 4:16 ` Michael Ellerman
2020-05-06 3:40 ` [PATCH v8 13/30] powerpc: Add a probe_user_read_inst() function Jordan Niethe
2020-05-13 12:52 ` Michael Ellerman
2020-05-13 23:51 ` Jordan Niethe
2020-05-14 5:46 ` Christophe Leroy
2020-05-15 3:46 ` Jordan Niethe
2020-05-06 3:40 ` [PATCH v8 14/30] powerpc: Add a probe_kernel_read_inst() function Jordan Niethe
2020-05-06 3:40 ` [PATCH v8 15/30] powerpc/kprobes: Use patch_instruction() Jordan Niethe
2020-05-06 3:40 ` [PATCH v8 16/30] powerpc: Define and use __get_user_instr{, inatomic}() Jordan Niethe
2020-05-13 14:18 ` Michael Ellerman
2020-05-13 23:54 ` Jordan Niethe
2020-05-14 1:43 ` Jordan Niethe
2020-05-06 3:40 ` [PATCH v8 17/30] powerpc: Introduce a function for reporting instruction length Jordan Niethe
2020-05-06 3:40 ` [PATCH v8 18/30] powerpc/xmon: Use a function for reading instructions Jordan Niethe
2020-05-06 3:40 ` [PATCH v8 19/30] powerpc/xmon: Move insertion of breakpoint for xol'ing Jordan Niethe
2020-05-06 3:40 ` [PATCH v8 20/30] powerpc: Make test_translate_branch() independent of instruction length Jordan Niethe
2020-05-06 3:40 ` Jordan Niethe [this message]
2020-05-06 3:40 ` [PATCH v8 22/30] powerpc: Define new SRR1 bits for a future ISA version Jordan Niethe
2020-05-08 2:26 ` Jordan Niethe
2020-05-06 3:40 ` [PATCH v8 23/30] powerpc: Add prefixed instructions to instruction data type Jordan Niethe
2020-05-14 1:40 ` Jordan Niethe
2020-05-14 6:11 ` Christophe Leroy
2020-05-14 12:06 ` Alistair Popple
2020-05-14 12:29 ` Jordan Niethe
2020-05-14 12:57 ` Christophe Leroy
2020-05-14 12:28 ` Jordan Niethe
2020-05-15 1:33 ` Michael Ellerman
2020-05-15 7:52 ` Jordan Niethe
2020-05-16 11:54 ` [PATCH v8 22.5/30] powerpc/optprobes: Add register argument to patch_imm64_load_insns() Michael Ellerman
2020-06-09 5:51 ` Michael Ellerman
2020-05-06 3:40 ` [PATCH v8 24/30] powerpc: Test prefixed code patching Jordan Niethe
2020-05-15 7:54 ` Jordan Niethe
2020-05-06 3:40 ` [PATCH v8 25/30] powerpc: Test prefixed instructions in feature fixups Jordan Niethe
2020-05-15 7:57 ` Jordan Niethe
2020-05-06 3:40 ` [PATCH v8 26/30] powerpc/xmon: Don't allow breakpoints on suffixes Jordan Niethe
2020-05-06 3:40 ` [PATCH v8 27/30] powerpc/kprobes: " Jordan Niethe
2021-05-18 18:43 ` Christophe Leroy
2021-05-18 19:52 ` Gabriel Paubert
2021-05-19 8:11 ` Naveen N. Rao
2021-05-20 3:45 ` Jordan Niethe
2020-05-06 3:40 ` [PATCH v8 28/30] powerpc: Support prefixed instructions in alignment handler Jordan Niethe
2020-05-14 6:14 ` Christophe Leroy
2020-05-14 12:15 ` Alistair Popple
2020-05-14 12:59 ` Christophe Leroy
2020-05-06 3:40 ` [PATCH v8 29/30] powerpc sstep: Add support for prefixed load/stores Jordan Niethe
2020-05-14 6:15 ` Christophe Leroy
2020-05-14 12:19 ` Alistair Popple
2020-05-14 13:00 ` Christophe Leroy
2020-05-15 7:59 ` Jordan Niethe
2020-05-06 3:40 ` [PATCH v8 30/30] powerpc sstep: Add support for prefixed fixed-point arithmetic Jordan Niethe
2020-05-14 6:15 ` Christophe Leroy
2020-05-15 8:02 ` Jordan Niethe
2020-05-14 5:31 ` [PATCH v8 00/30] Initial Prefixed Instruction support Christophe Leroy
2020-05-14 10:33 ` Jordan Niethe
2020-05-20 10:59 ` Michael Ellerman
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