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Wed, 22 Jul 2020 08:18:30 +0000 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 06M8IPLN61341790 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 22 Jul 2020 08:18:26 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D7E0511C05B; Wed, 22 Jul 2020 08:18:25 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5B3AE11C071; Wed, 22 Jul 2020 08:18:23 +0000 (GMT) Received: from linux.vnet.ibm.com (unknown [9.126.150.29]) by d06av25.portsmouth.uk.ibm.com (Postfix) with SMTP; Wed, 22 Jul 2020 08:18:23 +0000 (GMT) Date: Wed, 22 Jul 2020 13:48:22 +0530 From: Srikar Dronamraju To: peterz@infradead.org Subject: Re: [PATCH v2 06/10] powerpc/smp: Generalize 2nd sched domain Message-ID: <20200722081822.GG9290@linux.vnet.ibm.com> References: <20200721113814.32284-1-srikar@linux.vnet.ibm.com> <20200721113814.32284-7-srikar@linux.vnet.ibm.com> <20200722074624.GP119549@hirez.programming.kicks-ass.net> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline In-Reply-To: <20200722074624.GP119549@hirez.programming.kicks-ass.net> User-Agent: Mutt/1.10.1 (2018-07-13) X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-07-22_03:2020-07-22, 2020-07-22 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 mlxlogscore=999 impostorscore=0 mlxscore=0 suspectscore=1 bulkscore=0 clxscore=1015 spamscore=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2007220056 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Srikar Dronamraju Cc: Ingo Molnar , Nathan Lynch , Oliver OHalloran , Michael Neuling , Michael Ellerman , Gautham R Shenoy , Jordan Niethe , Anton Blanchard , LKML , Valentin Schneider , linuxppc-dev , Nick Piggin Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" * peterz@infradead.org [2020-07-22 09:46:24]: > On Tue, Jul 21, 2020 at 05:08:10PM +0530, Srikar Dronamraju wrote: > > Currently "CACHE" domain happens to be the 2nd sched domain as per > > powerpc_topology. This domain will collapse if cpumask of l2-cache is > > same as SMT domain. However we could generalize this domain such that it > > could mean either be a "CACHE" domain or a "BIGCORE" domain. > > What's the whole smallcore vs bigcore thing? > > Would it make sense to have an actual overview of the various topology > layers somewhere? Because I'm getting lost and can't really make sense > of the code due to that. To quote with an example: using (Power 9) Power 9 is an SMT 8 core by design. However this 8 thread core can run as 2 independent core with threads 0,2,4 and 6 acting like a core, while threads 1,3,5,7 acting as another core. The firmware can decide to showcase them as 2 independent small cores or as one big core. However the LLC (i.e last level of cache) is shared between all the threads of the SMT 8 core. Future power chips, LLC might change, it may be expanded to share with another SMT 8 core or it could be made specific to SMT 4 core. The smt 8 core is also known as fused core/ Big core. The smaller smt 4 core is known as small core. So on a Power9 Baremetal, the firmware would show up as SMT4 core. and we have a CACHE level at SMT 8. CACHE level would be very very similar to MC domain in X86. Hope this is clear. -- Thanks and Regards Srikar Dronamraju