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From: Ravi Bangoria <ravi.bangoria@linux.ibm.com>
To: mpe@ellerman.id.au
Cc: ravi.bangoria@linux.ibm.com, jniethe5@gmail.com,
	bala24@linux.ibm.com, paulus@samba.org, sandipan@linux.ibm.com,
	naveen.n.rao@linux.vnet.ibm.com, linuxppc-dev@lists.ozlabs.org
Subject: [PATCH v5 2/5] powerpc/sstep: Cover new VSX instructions under CONFIG_VSX
Date: Sun, 11 Oct 2020 10:39:05 +0530
Message-ID: <20201011050908.72173-3-ravi.bangoria@linux.ibm.com> (raw)
In-Reply-To: <20201011050908.72173-1-ravi.bangoria@linux.ibm.com>

Recently added Power10 prefixed VSX instruction are included
unconditionally in the kernel. If they are executed on a
machine without VSX support, it might create issues. Fix that.
Also fix one mnemonics spelling mistake in comment.

Fixes: 50b80a12e4cc ("powerpc sstep: Add support for prefixed load/stores")
Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.ibm.com>
---
 arch/powerpc/lib/sstep.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index e6242744c71b..faf0bbf3efb7 100644
--- a/arch/powerpc/lib/sstep.c
+++ b/arch/powerpc/lib/sstep.c
@@ -2757,6 +2757,7 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
 			case 41:	/* plwa */
 				op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 4);
 				break;
+#ifdef CONFIG_VSX
 			case 42:        /* plxsd */
 				op->reg = rd + 32;
 				op->type = MKOP(LOAD_VSX, PREFIXED, 8);
@@ -2797,13 +2798,14 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
 				op->element_size = 16;
 				op->vsx_flags = VSX_CHECK_VEC;
 				break;
+#endif /* CONFIG_VSX */
 			case 56:        /* plq */
 				op->type = MKOP(LOAD, PREFIXED, 16);
 				break;
 			case 57:	/* pld */
 				op->type = MKOP(LOAD, PREFIXED, 8);
 				break;
-			case 60:        /* stq */
+			case 60:        /* pstq */
 				op->type = MKOP(STORE, PREFIXED, 16);
 				break;
 			case 61:	/* pstd */
-- 
2.26.2


  parent reply index

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-11  5:09 [PATCH v5 0/5] powerpc/sstep: VSX 32-byte vector paired load/store instructions Ravi Bangoria
2020-10-11  5:09 ` [PATCH v5 1/5] powerpc/sstep: Emulate prefixed instructions only when CPU_FTR_ARCH_31 is set Ravi Bangoria
2020-10-11 15:06   ` Sandipan Das
2020-10-12  1:51   ` Daniel Axtens
2020-10-12 11:07     ` Ravi Bangoria
2020-10-12 12:55       ` Daniel Axtens
2020-10-12 13:44   ` Daniel Axtens
2020-10-14  7:34     ` Ravi Bangoria
2020-10-11  5:09 ` Ravi Bangoria [this message]
2020-10-11  5:09 ` [PATCH v5 3/5] powerpc/sstep: Support VSX vector paired storage access instructions Ravi Bangoria
2020-10-11  5:09 ` [PATCH v5 4/5] powerpc/ppc-opcode: Add encoding macros for VSX vector paired instructions Ravi Bangoria
2020-10-11  5:09 ` [PATCH v5 5/5] powerpc/sstep: Add testcases for VSX vector paired load/store instructions Ravi Bangoria
2020-12-15 10:49 ` [PATCH v5 0/5] powerpc/sstep: VSX 32-byte " Michael Ellerman

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