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From: "Michal Suchánek" <msuchanek@suse.de>
To: Madhavan Srinivasan <maddy@linux.ibm.com>
Cc: atrajeev@linux.vnet.ibm.com, linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH] powerpc/perf: fix Threshold Event CounterMultiplier width for P10
Date: Tue, 13 Oct 2020 17:58:42 +0200	[thread overview]
Message-ID: <20201013155842.GY29778@kitsune.suse.cz> (raw)
In-Reply-To: <b840fcf3-6546-159e-e23a-c8fe00123539@linux.ibm.com>

On Tue, Oct 13, 2020 at 06:27:05PM +0530, Madhavan Srinivasan wrote:
> 
> On 10/12/20 4:59 PM, Michal Suchánek wrote:
> > Hello,
> > 
> > On Mon, Oct 12, 2020 at 04:01:28PM +0530, Madhavan Srinivasan wrote:
> > > Power9 and isa v3.1 has 7bit mantissa field for Threshold Event Counter
> >                    ^^^ Shouldn't his be 3.0?
> 
> My bad, What I meant was
> 
> Power9, ISA v3.0 and ISA v3.1 define a 7 bit mantissa field for Threshold
> Event Counter Multiplier(TECM).
I am really confused.

The following text and the code suggests that the mantissa is 8bit on
POWER10 and ISA v3.1.

Thanks

Michal
> 
> Maddy
> 
> > 
> > > Multiplier (TECM). TECM is part of Monitor Mode Control Register A (MMCRA).
> > > This field along with Threshold Event Counter Exponent (TECE) is used to
> > > get threshould counter value. In Power10, the width of TECM field is
> > > increase to 8bits. Patch fixes the current code to modify the MMCRA[TECM]
> > > extraction macro to handling this changes.
> > > 
> > > Fixes: 170a315f41c64 ('powerpc/perf: Support to export MMCRA[TEC*] field to userspace')
> > > Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com>
> > > ---
> > >   arch/powerpc/perf/isa207-common.c | 3 +++
> > >   arch/powerpc/perf/isa207-common.h | 4 ++++
> > >   2 files changed, 7 insertions(+)
> > > 
> > > diff --git a/arch/powerpc/perf/isa207-common.c b/arch/powerpc/perf/isa207-common.c
> > > index 964437adec18..5fe129f02290 100644
> > > --- a/arch/powerpc/perf/isa207-common.c
> > > +++ b/arch/powerpc/perf/isa207-common.c
> > > @@ -247,6 +247,9 @@ void isa207_get_mem_weight(u64 *weight)
> > >   	u64 sier = mfspr(SPRN_SIER);
> > >   	u64 val = (sier & ISA207_SIER_TYPE_MASK) >> ISA207_SIER_TYPE_SHIFT;
> > > +	if (cpu_has_feature(CPU_FTR_ARCH_31))
> > > +		mantissa = P10_MMCRA_THR_CTR_MANT(mmcra);
> > > +
> > >   	if (val == 0 || val == 7)
> > >   		*weight = 0;
> > >   	else
> > > diff --git a/arch/powerpc/perf/isa207-common.h b/arch/powerpc/perf/isa207-common.h
> > > index 044de65e96b9..71380e854f48 100644
> > > --- a/arch/powerpc/perf/isa207-common.h
> > > +++ b/arch/powerpc/perf/isa207-common.h
> > > @@ -219,6 +219,10 @@
> > >   #define MMCRA_THR_CTR_EXP(v)		(((v) >> MMCRA_THR_CTR_EXP_SHIFT) &\
> > >   						MMCRA_THR_CTR_EXP_MASK)
> > > +#define P10_MMCRA_THR_CTR_MANT_MASK	0xFFul
> > > +#define P10_MMCRA_THR_CTR_MANT(v)	(((v) >> MMCRA_THR_CTR_MANT_SHIFT) &\
> > > +						P10_MMCRA_THR_CTR_MANT_MASK)
> > > +
> > >   /* MMCRA Threshold Compare bit constant for power9 */
> > >   #define p9_MMCRA_THR_CMP_SHIFT	45
> > > -- 
> > > 2.26.2
> > > 

  reply	other threads:[~2020-10-13 16:00 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-12 10:31 [PATCH] powerpc/perf: fix Threshold Event CounterMultiplier width for P10 Madhavan Srinivasan
2020-10-12 11:29 ` Michal Suchánek
2020-10-13 12:57   ` Madhavan Srinivasan
2020-10-13 15:58     ` Michal Suchánek [this message]
2020-10-14  5:50       ` Madhavan Srinivasan

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