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From: "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com>
To: linux-mm@kvack.org, akpm@linux-foundation.org
Cc: kaleshsingh@google.com, npiggin@gmail.com,
	"Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com>,
	joel@joelfernandes.org, linuxppc-dev@lists.ozlabs.org
Subject: [PATCH v3 4/9] powerpc/mm/book3s64: Fix possible build error
Date: Tue, 30 Mar 2021 11:37:47 +0530	[thread overview]
Message-ID: <20210330060752.592769-5-aneesh.kumar@linux.ibm.com> (raw)
In-Reply-To: <20210330060752.592769-1-aneesh.kumar@linux.ibm.com>

Update _tlbiel_pid() such that we can avoid build errors like below when
using this function in other places.

arch/powerpc/mm/book3s64/radix_tlb.c: In function ‘__radix__flush_tlb_range_psize’:
arch/powerpc/mm/book3s64/radix_tlb.c:114:2: warning: ‘asm’ operand 3 probably does not match constraints
  114 |  asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
      |  ^~~
arch/powerpc/mm/book3s64/radix_tlb.c:114:2: error: impossible constraint in ‘asm’
make[4]: *** [scripts/Makefile.build:271: arch/powerpc/mm/book3s64/radix_tlb.o] Error 1
m

With this fix, we can also drop the __always_inline in __radix_flush_tlb_range_psize
which was added by commit e12d6d7d46a6 ("powerpc/mm/radix: mark __radix__flush_tlb_range_psize() as __always_inline")

Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
---
 arch/powerpc/mm/book3s64/radix_tlb.c | 26 +++++++++++++++++---------
 1 file changed, 17 insertions(+), 9 deletions(-)

diff --git a/arch/powerpc/mm/book3s64/radix_tlb.c b/arch/powerpc/mm/book3s64/radix_tlb.c
index 409e61210789..817a02ef6032 100644
--- a/arch/powerpc/mm/book3s64/radix_tlb.c
+++ b/arch/powerpc/mm/book3s64/radix_tlb.c
@@ -291,22 +291,30 @@ static inline void fixup_tlbie_lpid(unsigned long lpid)
 /*
  * We use 128 set in radix mode and 256 set in hpt mode.
  */
-static __always_inline void _tlbiel_pid(unsigned long pid, unsigned long ric)
+static inline void _tlbiel_pid(unsigned long pid, unsigned long ric)
 {
 	int set;
 
 	asm volatile("ptesync": : :"memory");
 
-	/*
-	 * Flush the first set of the TLB, and if we're doing a RIC_FLUSH_ALL,
-	 * also flush the entire Page Walk Cache.
-	 */
-	__tlbiel_pid(pid, 0, ric);
+	switch (ric) {
+	case RIC_FLUSH_PWC:
 
-	/* For PWC, only one flush is needed */
-	if (ric == RIC_FLUSH_PWC) {
+		/* For PWC, only one flush is needed */
+		__tlbiel_pid(pid, 0, RIC_FLUSH_PWC);
 		ppc_after_tlbiel_barrier();
 		return;
+	case RIC_FLUSH_TLB:
+		__tlbiel_pid(pid, 0, RIC_FLUSH_TLB);
+		break;
+	case RIC_FLUSH_ALL:
+	default:
+		/*
+		 * Flush the first set of the TLB, and if
+		 * we're doing a RIC_FLUSH_ALL, also flush
+		 * the entire Page Walk Cache.
+		 */
+		__tlbiel_pid(pid, 0, RIC_FLUSH_ALL);
 	}
 
 	if (!cpu_has_feature(CPU_FTR_ARCH_31)) {
@@ -1176,7 +1184,7 @@ void radix__tlb_flush(struct mmu_gather *tlb)
 	}
 }
 
-static __always_inline void __radix__flush_tlb_range_psize(struct mm_struct *mm,
+static void __radix__flush_tlb_range_psize(struct mm_struct *mm,
 				unsigned long start, unsigned long end,
 				int psize, bool also_pwc)
 {
-- 
2.30.2


  parent reply	other threads:[~2021-03-30  6:10 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-30  6:07 [PATCH v3 0/9] Speedup mremap on ppc64 Aneesh Kumar K.V
2021-03-30  6:07 ` [PATCH v3 1/9] selftest/mremap_test: Update the test to handle pagesize other than 4K Aneesh Kumar K.V
2021-04-12 18:37   ` Kalesh Singh
2021-03-30  6:07 ` [PATCH v3 2/9] selftest/mremap_test: Avoid crash with static build Aneesh Kumar K.V
2021-04-12 18:38   ` Kalesh Singh
2021-03-30  6:07 ` [PATCH v3 3/9] mm/mremap: Use pmd/pud_poplulate to update page table entries Aneesh Kumar K.V
2021-03-30  6:07 ` Aneesh Kumar K.V [this message]
2021-04-09  9:15   ` [PATCH v3 4/9] powerpc/mm/book3s64: Fix possible build error Christophe Leroy
2021-03-30  6:07 ` [PATCH v3 5/9] powerpc/mm/book3s64: Update tlb flush routines to take a page walk cache flush argument Aneesh Kumar K.V
2021-03-30 13:28   ` kernel test robot
2021-04-09  9:18   ` Christophe Leroy
2021-03-30  6:07 ` [PATCH v3 6/9] mm/mremap: Use range flush that does TLB and page walk cache flush Aneesh Kumar K.V
2021-03-30  6:07 ` [PATCH v3 7/9] mm/mremap: Move TLB flush outside page table lock Aneesh Kumar K.V
2021-03-30  6:07 ` [PATCH v3 8/9] mm/mremap: Allow arch runtime override Aneesh Kumar K.V
2021-04-09  9:35   ` Christophe Leroy
2021-04-09 11:59     ` Aneesh Kumar K.V
2021-03-30  6:07 ` [PATCH v3 9/9] powerpc/mm: Enable move pmd/pud Aneesh Kumar K.V
2021-04-09  5:48 ` [PATCH v3 0/9] Speedup mremap on ppc64 Aneesh Kumar K.V

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