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From: Ben Widawsky <ben.widawsky@intel.com>
To: linux-cxl@vger.kernel.org
Cc: Ben Widawsky <ben.widawsky@intel.com>,
	Andrew Donnellan <ajd@linux.ibm.com>,
	linux-pci@vger.kernel.org, linuxppc-dev@lists.ozlabs.org,
	iommu@lists.linux-foundation.org,
	Bjorn Helgaas <helgaas@kernel.org>,
	"David E. Box" <david.e.box@linux.intel.com>,
	Frederic Barrat <fbarrat@linux.ibm.com>,
	Lu Baolu <baolu.lu@linux.intel.com>,
	David Woodhouse <dwmw2@infradead.org>,
	Kan Liang <kan.liang@linux.intel.com>
Subject: [PATCH v2 5/9] cxl/pci: Make more use of cxl_register_map
Date: Thu, 23 Sep 2021 10:26:43 -0700	[thread overview]
Message-ID: <20210923172647.72738-6-ben.widawsky@intel.com> (raw)
In-Reply-To: <20210923172647.72738-1-ben.widawsky@intel.com>

The structure exists to pass around information about register mapping.
Using it more extensively cleans up many existing functions.

Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
---
 drivers/cxl/cxl.h |  1 +
 drivers/cxl/pci.c | 36 +++++++++++++++++-------------------
 2 files changed, 18 insertions(+), 19 deletions(-)

diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 7d6b011dd963..3b128ce71564 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -140,6 +140,7 @@ struct cxl_device_reg_map {
 };
 
 struct cxl_register_map {
+	void __iomem *base;
 	u64 block_offset;
 	u8 reg_type;
 	u8 barno;
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index bbbacbc94fbf..5eaf2736f779 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -306,35 +306,36 @@ static int cxl_pci_setup_mailbox(struct cxl_mem *cxlm)
 	return 0;
 }
 
-static void __iomem *cxl_pci_map_regblock(struct cxl_mem *cxlm,
-					  u8 bar, u64 offset)
+static int cxl_pci_map_regblock(struct cxl_mem *cxlm, struct cxl_register_map *map)
 {
-	void __iomem *addr;
+	int bar = map->barno;
 	struct device *dev = cxlm->dev;
 	struct pci_dev *pdev = to_pci_dev(dev);
+	resource_size_t offset = map->block_offset;
 
 	/* Basic sanity check that BAR is big enough */
 	if (pci_resource_len(pdev, bar) < offset) {
 		dev_err(dev, "BAR%d: %pr: too small (offset: %#llx)\n", bar,
 			&pdev->resource[bar], (unsigned long long)offset);
-		return IOMEM_ERR_PTR(-ENXIO);
+		return -ENXIO;
 	}
 
-	addr = pci_iomap(pdev, bar, 0);
-	if (!addr) {
+	map->base = pci_iomap(pdev, bar, 0);
+	if (!map->base) {
 		dev_err(dev, "failed to map registers\n");
-		return addr;
+		return PTR_ERR(map->base);
 	}
 
 	dev_dbg(dev, "Mapped CXL Memory Device resource bar %u @ %#llx\n",
 		bar, offset);
 
-	return addr;
+	return 0;
 }
 
-static void cxl_pci_unmap_regblock(struct cxl_mem *cxlm, void __iomem *base)
+static void cxl_pci_unmap_regblock(struct cxl_mem *cxlm, struct cxl_register_map *map)
 {
-	pci_iounmap(to_pci_dev(cxlm->dev), base);
+	pci_iounmap(to_pci_dev(cxlm->dev), map->base);
+	map->base = 0;
 }
 
 static int cxl_pci_dvsec(struct pci_dev *pdev, int dvsec)
@@ -360,9 +361,9 @@ static int cxl_pci_dvsec(struct pci_dev *pdev, int dvsec)
 	return 0;
 }
 
-static int cxl_probe_regs(struct cxl_mem *cxlm, void __iomem *base,
-			  struct cxl_register_map *map)
+static int cxl_probe_regs(struct cxl_mem *cxlm, struct cxl_register_map *map)
 {
+	void __iomem *base = map->base + map->block_offset;
 	struct cxl_component_reg_map *comp_map;
 	struct cxl_device_reg_map *dev_map;
 	struct device *dev = cxlm->dev;
@@ -487,7 +488,6 @@ static int cxl_pci_setup_regs(struct cxl_mem *cxlm)
 
 	for (i = 0; i < ARRAY_SIZE(types); i++) {
 		struct cxl_register_map map;
-		void __iomem *base;
 
 		rc = find_register_block(pdev, types[i], &map);
 		if (rc) {
@@ -498,14 +498,12 @@ static int cxl_pci_setup_regs(struct cxl_mem *cxlm)
 			break;
 		}
 
-		base = cxl_pci_map_regblock(cxlm, map.barno, map.block_offset);
-		if (!base) {
-			rc = -ENOMEM;
+		rc = cxl_pci_map_regblock(cxlm, &map);
+		if (rc)
 			break;
-		}
 
-		rc = cxl_probe_regs(cxlm, base + map.block_offset, &map);
-		cxl_pci_unmap_regblock(cxlm, base);
+		rc = cxl_probe_regs(cxlm, &map);
+		cxl_pci_unmap_regblock(cxlm, &map);
 		if (rc)
 			break;
 
-- 
2.33.0


  parent reply	other threads:[~2021-09-23 17:32 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-23 17:26 [PATCH v2 0/9] cxl_pci refactor for reusability Ben Widawsky
2021-09-23 17:26 ` [PATCH v2 1/9] cxl: Convert "RBI" to enum Ben Widawsky
2021-09-27 23:13   ` Dan Williams
2021-09-23 17:26 ` [PATCH v2 2/9] cxl/pci: Remove dev_dbg for unknown register blocks Ben Widawsky
2021-09-28 14:37   ` Dan Williams
2021-09-23 17:26 ` [PATCH v2 3/9] cxl/pci: Remove pci request/release regions Ben Widawsky
2021-09-28 14:42   ` Dan Williams
2021-09-23 17:26 ` [PATCH v2 4/9] cxl/pci: Refactor cxl_pci_setup_regs Ben Widawsky
2021-09-28 17:35   ` Dan Williams
2021-09-23 17:26 ` Ben Widawsky [this message]
2021-09-28 17:41   ` [PATCH v2 5/9] cxl/pci: Make more use of cxl_register_map Dan Williams
2021-09-23 17:26 ` [PATCH v2 6/9] PCI: Add pci_find_dvsec_capability to find designated VSEC Ben Widawsky
2021-09-23 21:37   ` Liang, Kan
2021-09-27 17:46   ` Bjorn Helgaas
2021-09-28  5:50   ` Andrew Donnellan
2021-10-01  9:42   ` Jonathan Cameron
2021-09-23 17:26 ` [PATCH v2 7/9] cxl/pci: Use pci core's DVSEC functionality Ben Widawsky
2021-09-28 17:43   ` Dan Williams
2021-09-23 17:26 ` [PATCH v2 8/9] ocxl: " Ben Widawsky
2021-09-28  5:52   ` Andrew Donnellan
2021-09-23 17:26 ` [PATCH v2 9/9] iommu/vt-d: " Ben Widawsky
2021-09-24  6:42   ` Christoph Hellwig
2021-09-28 17:54   ` Dan Williams
2021-09-29  1:36     ` Lu Baolu

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