From: Chen Zhongjin <chenzhongjin@huawei.com>
To: <linux-kernel@vger.kernel.org>, <linux-arch@vger.kernel.org>,
<linuxppc-dev@lists.ozlabs.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kbuild@vger.kernel.org>, <live-patching@vger.kernel.org>
Cc: mark.rutland@arm.com, madvenka@linux.microsoft.com,
daniel.thompson@linaro.org, michal.lkml@markovi.net,
pasha.tatashin@soleen.com, peterz@infradead.org,
catalin.marinas@arm.com, masahiroy@kernel.org,
ndesaulniers@google.com, chenzhongjin@huawei.com,
rmk+kernel@armlinux.org.uk, broonie@kernel.org, will@kernel.org,
jpoimboe@kernel.org
Subject: [PATCH v6 03/33] objtool: arm64: Decode add/sub instructions
Date: Thu, 23 Jun 2022 09:48:47 +0800 [thread overview]
Message-ID: <20220623014917.199563-4-chenzhongjin@huawei.com> (raw)
In-Reply-To: <20220623014917.199563-1-chenzhongjin@huawei.com>
Decode aarch64 additions and substractions and create stack_ops for
instructions interacting with SP or FP.
Signed-off-by: Julien Thierry <jthierry@redhat.com>
Signed-off-by: Chen Zhongjin <chenzhongjin@huawei.com>
---
tools/objtool/arch/arm64/decode.c | 82 +++++++++++++++++++++++++++++++
1 file changed, 82 insertions(+)
diff --git a/tools/objtool/arch/arm64/decode.c b/tools/objtool/arch/arm64/decode.c
index afe22c4593c8..d8c32703874d 100644
--- a/tools/objtool/arch/arm64/decode.c
+++ b/tools/objtool/arch/arm64/decode.c
@@ -15,6 +15,22 @@
#include "../../../arch/arm64/lib/insn.c"
+#define is_SP(reg) (reg == AARCH64_INSN_REG_SP)
+#define is_FP(reg) (reg == AARCH64_INSN_REG_FP)
+#define is_SPFP(reg) (reg == AARCH64_INSN_REG_SP || reg == AARCH64_INSN_REG_FP)
+
+#define ADD_OP(op) \
+ if (!(op = calloc(1, sizeof(*op)))) \
+ return -1; \
+ else for (list_add_tail(&op->list, ops_list); op; op = NULL)
+
+static unsigned long sign_extend(unsigned long x, int nbits)
+{
+ unsigned long sign_bit = (x >> (nbits - 1)) & 1;
+
+ return ((~0UL + (sign_bit ^ 1)) << nbits) | x;
+}
+
bool arch_callee_saved_reg(unsigned char reg)
{
switch (reg) {
@@ -105,6 +121,42 @@ int arch_decode_hint_reg(u8 sp_reg, int *base)
return -1;
}
+static inline void make_add_op(enum aarch64_insn_register dest,
+ enum aarch64_insn_register src,
+ int val, struct stack_op *op)
+{
+ op->dest.type = OP_DEST_REG;
+ op->dest.reg = dest;
+ op->src.reg = src;
+ op->src.type = val != 0 ? OP_SRC_ADD : OP_SRC_REG;
+ op->src.offset = val;
+}
+
+static void decode_add_sub_imm(u32 instr, bool set_flags,
+ unsigned long *immediate,
+ struct stack_op *op)
+{
+ u32 rd = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RD, instr);
+ u32 rn = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RN, instr);
+
+ *immediate = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_12, instr);
+
+ if (instr & AARCH64_INSN_LSL_12)
+ *immediate <<= 12;
+
+ if ((!set_flags && is_SP(rd)) || is_FP(rd)
+ || is_SPFP(rn)) {
+ int value;
+
+ if (aarch64_insn_is_subs_imm(instr) || aarch64_insn_is_sub_imm(instr))
+ value = -*immediate;
+ else
+ value = *immediate;
+
+ make_add_op(rd, rn, value, op);
+ }
+}
+
int arch_decode_instruction(struct objtool_file *file, const struct section *sec,
unsigned long offset, unsigned int maxlen,
unsigned int *len, enum insn_type *type,
@@ -112,6 +164,7 @@ int arch_decode_instruction(struct objtool_file *file, const struct section *sec
struct list_head *ops_list)
{
const struct elf *elf = file->elf;
+ struct stack_op *op = NULL;
u32 insn;
if (!is_arm64(elf))
@@ -130,6 +183,35 @@ int arch_decode_instruction(struct objtool_file *file, const struct section *sec
case AARCH64_INSN_CLS_UNKNOWN:
WARN("can't decode instruction at %s:0x%lx", sec->name, offset);
return -1;
+ case AARCH64_INSN_CLS_DP_IMM:
+ /* Mov register to and from SP are aliases of add_imm */
+ if (aarch64_insn_is_add_imm(insn) ||
+ aarch64_insn_is_sub_imm(insn)) {
+ ADD_OP(op) {
+ decode_add_sub_imm(insn, false, immediate, op);
+ }
+ }
+ else if (aarch64_insn_is_adds_imm(insn) ||
+ aarch64_insn_is_subs_imm(insn)) {
+ ADD_OP(op) {
+ decode_add_sub_imm(insn, true, immediate, op);
+ }
+ }
+ break;
+ case AARCH64_INSN_CLS_DP_REG:
+ if (aarch64_insn_is_mov_reg(insn)) {
+ enum aarch64_insn_register rd;
+ enum aarch64_insn_register rm;
+
+ rd = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RD, insn);
+ rm = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RM, insn);
+ if (is_FP(rd) || is_FP(rm)) {
+ ADD_OP(op) {
+ make_add_op(rd, rm, 0, op);
+ }
+ }
+ }
+ break;
default:
break;
}
--
2.17.1
next prev parent reply other threads:[~2022-06-23 1:52 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-23 1:48 [PATCH v5 00/33] objtool: add base support for arm64 Chen Zhongjin
2022-06-23 1:48 ` [PATCH v6 01/33] tools: arm64: Make aarch64 instruction decoder available to tools Chen Zhongjin
2022-06-23 1:48 ` [PATCH v6 02/33] objtool: arm64: Add base definition for arm64 backend Chen Zhongjin
2022-06-23 1:48 ` Chen Zhongjin [this message]
2022-06-23 1:48 ` [PATCH v6 04/33] objtool: arm64: Decode jump and call related instructions Chen Zhongjin
2022-06-23 1:48 ` [PATCH v6 05/33] objtool: arm64: Decode other system instructions Chen Zhongjin
2022-06-23 1:48 ` [PATCH v6 06/33] objtool: arm64: Decode load/store instructions Chen Zhongjin
2022-06-23 1:48 ` [PATCH v6 07/33] objtool: arm64: Decode LDR instructions Chen Zhongjin
2022-06-23 1:48 ` [PATCH v6 08/33] objtool: arm64: Accept non-instruction data in code sections Chen Zhongjin
2022-06-23 1:48 ` [PATCH v6 09/33] objtool: check: Support data in text section Chen Zhongjin
2022-06-23 1:48 ` [PATCH v6 10/33] objtool: arm64: Handle supported relocations in alternatives Chen Zhongjin
2022-06-23 1:48 ` [PATCH v6 11/33] objtool: arm64: Ignore replacement section for alternative callback Chen Zhongjin
2022-06-23 1:48 ` [PATCH v6 12/33] objtool: arm64: Enable stack validation for arm64 Chen Zhongjin
2022-06-23 1:48 ` [PATCH v6 13/33] objtool: arm64: Enable ORC " Chen Zhongjin
2022-06-23 1:48 ` [PATCH v6 14/33] objtool: arm64: Add annotate_reachable() for objtools Chen Zhongjin
2022-06-23 1:48 ` [PATCH v6 15/33] arm64: bug: Add reachable annotation to warning macros Chen Zhongjin
2022-06-23 1:49 ` [PATCH v6 16/33] arm64: kgdb: Add reachable annotation after kgdb brk Chen Zhongjin
2022-06-23 1:49 ` [PATCH v6 17/33] objtool: arm64: Add unwind_hint support Chen Zhongjin
2022-06-23 1:49 ` [PATCH v6 18/33] arm64: Change symbol type annotations Chen Zhongjin
2022-06-29 17:47 ` Mark Brown
2022-06-30 2:41 ` Chen Zhongjin
2022-06-23 1:49 ` [PATCH v6 19/33] arm64: Annotate unwind_hint for symbols with empty stack Chen Zhongjin
2022-06-23 1:49 ` [PATCH v6 20/33] arm64: entry: Annotate unwind_hint for entry Chen Zhongjin
2022-06-23 1:49 ` [PATCH v6 21/33] arm64: kvm: Annotate unwind_hint for hyp entry Chen Zhongjin
2022-06-23 1:49 ` [PATCH v6 22/33] arm64: efi-header: Mark efi header as data Chen Zhongjin
2022-06-29 18:03 ` Mark Brown
2022-06-23 1:49 ` [PATCH v6 23/33] arm64: head: Mark constants " Chen Zhongjin
2022-06-23 1:49 ` [PATCH v6 24/33] arm64: proc: Mark constant " Chen Zhongjin
2022-06-29 18:06 ` Mark Brown
2022-06-23 1:49 ` [PATCH v6 25/33] arm64: crypto: " Chen Zhongjin
2022-06-29 18:20 ` Mark Brown
2022-06-23 1:49 ` [PATCH v6 26/33] arm64: crypto: Remove unnecessary stackframe Chen Zhongjin
2022-06-23 1:49 ` [PATCH v6 27/33] arm64: Set intra-function call annotations Chen Zhongjin
2022-06-23 1:49 ` [PATCH v6 28/33] arm64: sleep: Properly set frame pointer before call Chen Zhongjin
2022-06-23 1:49 ` [PATCH v6 29/33] arm64: compat: Move VDSO code to .rodata section Chen Zhongjin
2022-06-23 1:49 ` [PATCH v6 30/33] arm64: entry: Align stack size for alternative Chen Zhongjin
2022-06-23 1:49 ` [PATCH v6 31/33] arm64: kernel: Skip validation of proton-pack.c Chen Zhongjin
2022-06-23 1:49 ` [PATCH v6 32/33] arm64: irq-gic: Replace unreachable() with -EINVAL Chen Zhongjin
2022-06-23 8:13 ` Marc Zyngier
2022-06-24 1:24 ` Chen Zhongjin
2022-06-23 1:49 ` [PATCH v6 33/33] objtool: revert c_file fallthrough detection for arm64 Chen Zhongjin
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