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From: Rohan McLure <rmclure@linux.ibm.com>
To: linuxppc-dev@lists.ozlabs.org
Cc: Rohan McLure <rmclure@linux.ibm.com>, npiggin@gmail.com
Subject: [PATCH v4 4/7] powerpc/64s: IOption for MSR stored in r12
Date: Tue, 29 Nov 2022 15:43:51 +1100	[thread overview]
Message-ID: <20221129044354.1836018-4-rmclure@linux.ibm.com> (raw)
In-Reply-To: <20221129044354.1836018-1-rmclure@linux.ibm.com>

Interrupt handlers in asm/exceptions-64s.S contain a great deal of common
code produced by the GEN_COMMON macros. Currently, at the exit point of
the macro, r12 will contain the contents of the MSR. A future patch will
cause these macros to zeroise architected registers to avoid potential
speculation influence of user data.

Provide an IOption that signals that r12 must be retained, as the
interrupt handler assumes it to hold the contents of the MSR.

Signed-off-by: Rohan McLure <rmclure@linux.ibm.com>
---
v4: Split 64s register sanitisation commit to establish this IOption
---
 arch/powerpc/kernel/exceptions-64s.S | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 5381a43e50fe..58d72db1d484 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -111,6 +111,7 @@ name:
 #define ISTACK		.L_ISTACK_\name\()	/* Set regular kernel stack */
 #define __ISTACK(name)	.L_ISTACK_ ## name
 #define IKUAP		.L_IKUAP_\name\()	/* Do KUAP lock */
+#define IMSR_R12	.L_IMSR_R12_\name\()	/* Assumes MSR saved to r12 */
 
 #define INT_DEFINE_BEGIN(n)						\
 .macro int_define_ ## n name
@@ -176,6 +177,9 @@ do_define_int n
 	.ifndef IKUAP
 		IKUAP=1
 	.endif
+	.ifndef IMSR_R12
+		IMSR_R12=0
+	.endif
 .endm
 
 /*
@@ -1751,6 +1755,7 @@ INT_DEFINE_BEGIN(fp_unavailable)
 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
 	IKVM_REAL=1
 #endif
+	IMSR_R12=1
 INT_DEFINE_END(fp_unavailable)
 
 EXC_REAL_BEGIN(fp_unavailable, 0x800, 0x100)
@@ -2372,6 +2377,7 @@ INT_DEFINE_BEGIN(altivec_unavailable)
 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
 	IKVM_REAL=1
 #endif
+	IMSR_R12=1
 INT_DEFINE_END(altivec_unavailable)
 
 EXC_REAL_BEGIN(altivec_unavailable, 0xf20, 0x20)
@@ -2421,6 +2427,7 @@ INT_DEFINE_BEGIN(vsx_unavailable)
 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
 	IKVM_REAL=1
 #endif
+	IMSR_R12=1
 INT_DEFINE_END(vsx_unavailable)
 
 EXC_REAL_BEGIN(vsx_unavailable, 0xf40, 0x20)
-- 
2.37.2


  parent reply	other threads:[~2022-11-29  4:47 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-29  4:43 [PATCH v4 1/7] powerpc/64: Add INTERRUPT_SANITIZE_REGISTERS Kconfig Rohan McLure
2022-11-29  4:43 ` [PATCH v4 2/7] powerpc/64: Add interrupt register sanitisation macros Rohan McLure
2022-11-29  9:40   ` Nicholas Piggin
2022-11-29  4:43 ` [PATCH v4 3/7] powerpc/64: Sanitise common exit code for interrupts Rohan McLure
2022-11-29  9:46   ` Nicholas Piggin
2022-11-29  4:43 ` Rohan McLure [this message]
2022-11-29  9:48   ` [PATCH v4 4/7] powerpc/64s: IOption for MSR stored in r12 Nicholas Piggin
2022-11-29  4:43 ` [PATCH v4 5/7] powerpc/64s: Zeroise gprs on interrupt routine entry on Book3S Rohan McLure
2022-11-29 10:20   ` Nicholas Piggin
2022-11-29  4:43 ` [PATCH v4 6/7] powerpc/64e: Clear gprs on interrupt routine entry on Book3E Rohan McLure
2022-11-29  4:43 ` [PATCH v4 7/7] powerpc/64: Sanitise user registers on interrupt in pseries, POWERNV Rohan McLure
2022-11-29 10:21   ` Nicholas Piggin

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