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Tue, 17 May 2022 14:06:28 +0000 (GMT) Content-Type: text/plain; charset=us-ascii Mime-Version: 1.0 (Mac OS X Mail 14.0 \(3654.120.0.1.13\)) Subject: Re: [PATCH 2/2] powerpc/perf: Fix the threshold compare group constraint for power9 From: Athira Rajeev In-Reply-To: <20220506061015.43916-2-kjain@linux.ibm.com> Date: Tue, 17 May 2022 19:36:24 +0530 Content-Transfer-Encoding: quoted-printable Message-Id: <2E9D3C37-F4FB-4480-B007-49E1ABD0A36D@linux.vnet.ibm.com> References: <20220506061015.43916-1-kjain@linux.ibm.com> <20220506061015.43916-2-kjain@linux.ibm.com> To: Kajol Jain X-Mailer: Apple Mail (2.3654.120.0.1.13) X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: DcY6Cm88DgH1KVyWvr_4O5j0L4yQMHC4 X-Proofpoint-GUID: DcY6Cm88DgH1KVyWvr_4O5j0L4yQMHC4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-17_03,2022-05-17_02,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 lowpriorityscore=0 spamscore=0 phishscore=0 priorityscore=1501 clxscore=1015 impostorscore=0 mlxscore=0 mlxlogscore=999 suspectscore=0 malwarescore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2202240000 definitions=main-2205170087 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Madhavan Srinivasan , linuxppc-dev@lists.ozlabs.org, disgoel@linux.vnet.ibm.com, Nageswara Sastry Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" > On 06-May-2022, at 11:40 AM, Kajol Jain wrote: >=20 > Thresh compare bits for a event is used to program thresh compare > field in Monitor Mode Control Register A (MMCRA: 9-18 bits for = power9). > When scheduling events as a group, all events in that group should > match value in threshold bits (like thresh compare, thresh control, > thresh select). Otherwise event open for the sibling events should = fail. > But in the current code, incase thresh compare bits are not valid, > we are not failing in group_constraint function which can result > in invalid group schduling. >=20 > Fix the issue by returning -1 incase event is threshold and threshold > compare value is not valid. >=20 > Thresh control bits in the event code is used to program thresh_ctl > field in Monitor Mode Control Register A (MMCRA: 48-55). In below = example, > the scheduling of group events PM_MRK_INST_CMPL (873534401e0) and > PM_THRESH_MET (8734340101ec) is expected to fail as both event > request different thresh control bits and invalid thresh compare = value. >=20 > Result before the patch changes: >=20 > [command]# perf stat -e "{r8735340401e0,r8734340101ec}" sleep 1 >=20 > Performance counter stats for 'sleep 1': >=20 > 11,048 r8735340401e0 > 1,967 r8734340101ec >=20 > 1.001354036 seconds time elapsed >=20 > 0.001421000 seconds user > 0.000000000 seconds sys >=20 > Result after the patch changes: >=20 > [command]# perf stat -e "{r8735340401e0,r8734340101ec}" sleep 1 > Error: > The sys_perf_event_open() syscall returned with 22 (Invalid argument) > for event (r8735340401e0). > /bin/dmesg | grep -i perf may provide additional information. >=20 > Fixes: 78a16d9fc1206 ("powerpc/perf: Avoid FAB_*_MATCH checks for = power9") > Signed-off-by: Kajol Jain Reviewed-by: Athira Rajeev Thanks Athira > --- > arch/powerpc/perf/isa207-common.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) >=20 > diff --git a/arch/powerpc/perf/isa207-common.c = b/arch/powerpc/perf/isa207-common.c > index 013b06af6fe6..bb5d64862bc9 100644 > --- a/arch/powerpc/perf/isa207-common.c > +++ b/arch/powerpc/perf/isa207-common.c > @@ -508,7 +508,8 @@ int isa207_get_constraint(u64 event, unsigned long = *maskp, unsigned long *valp, > if (event_is_threshold(event) && = is_thresh_cmp_valid(event)) { > mask |=3D CNST_THRESH_MASK; > value |=3D CNST_THRESH_VAL(event >> = EVENT_THRESH_SHIFT); > - } > + } else if (event_is_threshold(event)) > + return -1; > } else { > /* > * Special case for PM_MRK_FAB_RSP_MATCH and = PM_MRK_FAB_RSP_MATCH_CYC, > --=20 > 2.31.1 >=20