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b=nSaeQ4M43qkszTtASKAZliUvDS4okaQxAwD1k8WyCfl+lTAjNJ4LaG/LQHwlI2LgbC EBB/WTKQ4gNi/PhrN1yeD22MCYxoI4fww8PKqJjQIGyRcNEg5mmyPE/yo83KZVIuLCPq eCMBlG2VQ0p5c+EzgiRWCYsq6OKfpPg5DdfHoJbfsmWfCUVYfII5gXrlsUkM9SJiqEyV OiB69vNDj9MlL4xP8dPvvoiLFuCgygEQtnwDkR6kAdUls2LVj+WOs8O20k+MRnbPpa6g IfgNxz7DINcoY6udbyR8jpgB7FmzbYWe6IaewdX8hqO6WpGs1NM51nNl7aFtXRWkq5tX f9Lw== X-Gm-Message-State: AOAM5332FYM1n5xjWLbGRJFb8bzv0hnprOkomLO28iRotjTy7azvbFN8 g7hYL99lGvLf7cmSTb9ZGTU= X-Google-Smtp-Source: ABdhPJxFhinlHNn02trTin40jfBumlNTfk5ie7OrDNyXW4/JI/YC1pS+0OjO1mDC9iZf7UePRpjcKg== X-Received: by 2002:a37:d4e:: with SMTP id 75mr1110422qkn.457.1618606685688; Fri, 16 Apr 2021 13:58:05 -0700 (PDT) Received: from li-908e0a4c-2250-11b2-a85c-f027e903211b.ibm.com ([177.35.200.187]) by smtp.gmail.com with ESMTPSA id n15sm4860020qkk.109.2021.04.16.13.58.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Apr 2021 13:58:05 -0700 (PDT) Message-ID: <7b089cd48b90f2445c7cb80da1ce8638607c46fc.camel@gmail.com> Subject: Re: [PATCH 1/1] of/pci: Add IORESOURCE_MEM_64 to resource flags for 64-bit memory addresses From: Leonardo Bras To: Rob Herring Date: Fri, 16 Apr 2021 17:57:59 -0300 In-Reply-To: References: <20210415180050.373791-1-leobras.c@gmail.com> Organization: IBM Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.38.4 (3.38.4-1.fc33) MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Alexey Kardashevskiy , Frank Rowand , "linux-kernel@vger.kernel.org" , PCI , linuxppc-dev Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Hello Rob, thanks for this feedback! On Thu, 2021-04-15 at 13:59 -0500, Rob Herring wrote: > +PPC and PCI lists > > On Thu, Apr 15, 2021 at 1:01 PM Leonardo Bras wrote: > > > > Many other resource flag parsers already add this flag when the input > > has bits 24 & 25 set, so update this one to do the same. > > Many others? Looks like sparc and powerpc to me.  > s390 also does that, but it look like it comes from a device-tree. > Those would be the > ones I worry about breaking. Sparc doesn't use of/address.c so it's > fine. Powerpc version of the flags code was only fixed in 2019, so I > don't think powerpc will care either. In powerpc I reach this function with this stack, while configuring a virtio-net device for a qemu/KVM pseries guest: pci_process_bridge_OF_ranges+0xac/0x2d4 pSeries_discover_phbs+0xc4/0x158 discover_phbs+0x40/0x60 do_one_initcall+0x60/0x2d0 kernel_init_freeable+0x308/0x3a8 kernel_init+0x2c/0x168 ret_from_kernel_thread+0x5c/0x70 For this, both MMIO32 and MMIO64 resources will have flags 0x200. > > I noticed both sparc and powerpc set PCI_BASE_ADDRESS_MEM_TYPE_64 in > the flags. AFAICT, that's not set anywhere outside of arch code. So > never for riscv, arm and arm64 at least. That leads me to > pci_std_update_resource() which is where the PCI code sets BARs and > just copies the flags in PCI_BASE_ADDRESS_MEM_MASK ignoring > IORESOURCE_* flags. So it seems like 64-bit is still not handled and > neither is prefetch. > I am not sure if you mean here: a) it's ok to add IORESOURCE_MEM_64 here, because it does not affect anything else, or b) it should be using PCI_BASE_ADDRESS_MEM_TYPE_64  (or IORESOURCE_MEM_64 | PCI_BASE_ADDRESS_MEM_TYPE_64) instead, since it's how it's added in powerpc/sparc, and else there is no point. Again, thanks for helping! Best regards, Leonardo Bras