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[200.158.48.188]) by smtp.gmail.com with ESMTPSA id 17sm1544028qtr.65.2019.06.06.12.39.06 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 06 Jun 2019 12:39:07 -0700 (PDT) From: Murilo Opsfelder =?utf-8?Q?Ara=C3=BAjo?= To: Claudio Carvalho , linuxppc-dev@ozlabs.org Subject: Re: [PATCH v3 6/9] KVM: PPC: Ultravisor: Restrict flush of the partition tlb cache In-Reply-To: <20190606173614.32090-7-cclaudio@linux.ibm.com> References: <20190606173614.32090-1-cclaudio@linux.ibm.com> <20190606173614.32090-7-cclaudio@linux.ibm.com> Date: Thu, 06 Jun 2019 16:39:04 -0300 Message-ID: <8736kmld0n.fsf@kermit.br.ibm.com> MIME-Version: 1.0 Content-Type: text/plain X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: , Madhavan Srinivasan , Michael Anderson , Ram Pai , Claudio Carvalho , kvm-ppc@vger.kernel.org, Bharata B Rao , Sukadev Bhattiprolu , Thiago Bauermann , Anshuman Khandual Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Claudio Carvalho writes: > From: Ram Pai > > Ultravisor is responsible for flushing the tlb cache, since it manages > the PATE entries. Hence skip tlb flush, if the ultravisor firmware is > available. > > Signed-off-by: Ram Pai > Signed-off-by: Claudio Carvalho > --- > arch/powerpc/mm/book3s64/pgtable.c | 33 +++++++++++++++++------------- > 1 file changed, 19 insertions(+), 14 deletions(-) > > diff --git a/arch/powerpc/mm/book3s64/pgtable.c b/arch/powerpc/mm/book3s64/pgtable.c > index 40a9fc8b139f..1eeb5fe87023 100644 > --- a/arch/powerpc/mm/book3s64/pgtable.c > +++ b/arch/powerpc/mm/book3s64/pgtable.c > @@ -224,6 +224,23 @@ void __init mmu_partition_table_init(void) > powernv_set_nmmu_ptcr(ptcr); > } > > +static void flush_partition(unsigned int lpid, unsigned long dw0) > +{ > + if (dw0 & PATB_HR) { > + asm volatile(PPC_TLBIE_5(%0, %1, 2, 0, 1) : : > + "r" (TLBIEL_INVAL_SET_LPID), "r" (lpid)); > + asm volatile(PPC_TLBIE_5(%0, %1, 2, 1, 1) : : > + "r" (TLBIEL_INVAL_SET_LPID), "r" (lpid)); > + trace_tlbie(lpid, 0, TLBIEL_INVAL_SET_LPID, lpid, 2, 0, 1); > + } else { > + asm volatile(PPC_TLBIE_5(%0, %1, 2, 0, 0) : : > + "r" (TLBIEL_INVAL_SET_LPID), "r" (lpid)); > + trace_tlbie(lpid, 0, TLBIEL_INVAL_SET_LPID, lpid, 2, 0, 0); > + } > + /* do we need fixup here ?*/ > + asm volatile("eieio; tlbsync; ptesync" : : : "memory"); > +} > + checkpatch.pl seems to complain: ERROR: need consistent spacing around '%' (ctx:WxV) #125: FILE: arch/powerpc/mm/book3s64/pgtable.c:230: + asm volatile(PPC_TLBIE_5(%0, %1, 2, 0, 1) : : ^ ERROR: need consistent spacing around '%' (ctx:WxV) #127: FILE: arch/powerpc/mm/book3s64/pgtable.c:232: + asm volatile(PPC_TLBIE_5(%0, %1, 2, 1, 1) : : ^ ERROR: need consistent spacing around '%' (ctx:WxV) #131: FILE: arch/powerpc/mm/book3s64/pgtable.c:236: + asm volatile(PPC_TLBIE_5(%0, %1, 2, 0, 0) : : ^ > static void __mmu_partition_table_set_entry(unsigned int lpid, > unsigned long dw0, > unsigned long dw1) > @@ -238,20 +255,8 @@ static void __mmu_partition_table_set_entry(unsigned int lpid, > * The type of flush (hash or radix) depends on what the previous > * use of this partition ID was, not the new use. > */ > - asm volatile("ptesync" : : : "memory"); > - if (old & PATB_HR) { > - asm volatile(PPC_TLBIE_5(%0,%1,2,0,1) : : > - "r" (TLBIEL_INVAL_SET_LPID), "r" (lpid)); > - asm volatile(PPC_TLBIE_5(%0,%1,2,1,1) : : > - "r" (TLBIEL_INVAL_SET_LPID), "r" (lpid)); > - trace_tlbie(lpid, 0, TLBIEL_INVAL_SET_LPID, lpid, 2, 0, 1); > - } else { > - asm volatile(PPC_TLBIE_5(%0,%1,2,0,0) : : > - "r" (TLBIEL_INVAL_SET_LPID), "r" (lpid)); > - trace_tlbie(lpid, 0, TLBIEL_INVAL_SET_LPID, lpid, 2, 0, 0); > - } > - /* do we need fixup here ?*/ > - asm volatile("eieio; tlbsync; ptesync" : : : "memory"); > + if (!firmware_has_feature(FW_FEATURE_ULTRAVISOR)) > + flush_partition(lpid, old); > } > > void mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0, > -- > 2.20.1