From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 643DBC43387 for ; Thu, 10 Jan 2019 13:17:12 +0000 (UTC) Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9D64F214DA for ; Thu, 10 Jan 2019 13:17:11 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9D64F214DA Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=ellerman.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 43b63T4W6ZzDqgq for ; Fri, 11 Jan 2019 00:17:09 +1100 (AEDT) Received: from ozlabs.org (bilbo.ozlabs.org [IPv6:2401:3900:2:1::2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 43b61N6qfmzDqfB for ; Fri, 11 Jan 2019 00:15:20 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=ellerman.id.au Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPSA id 43b61H3QY0z9sLt; Fri, 11 Jan 2019 00:15:15 +1100 (AEDT) From: Michael Ellerman To: Peter Zijlstra , Andrew Murray Subject: Re: [PATCH v4 10/13] x86: perf/core: use PERF_PMU_CAP_NO_EXCLUDE for exclude incapable PMUs In-Reply-To: <20190108104841.GD6808@hirez.programming.kicks-ass.net> References: <1546878450-20341-1-git-send-email-andrew.murray@arm.com> <1546878450-20341-11-git-send-email-andrew.murray@arm.com> <20190108104841.GD6808@hirez.programming.kicks-ass.net> Date: Fri, 11 Jan 2019 00:15:13 +1100 Message-ID: <87ef9kslge.fsf@concordia.ellerman.id.au> MIME-Version: 1.0 Content-Type: text/plain X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Will Deacon , Paul Mackerras , Shawn Guo , Thomas Gleixner , x86@kernel.org, Russell King , Ingo Molnar , Matt Turner , suzuki.poulose@arm.com, Sascha Hauer , Arnaldo Carvalho de Melo , Ivan Kokshaysky , boris.ostrovsky@oracle.com, linux-arm-kernel@lists.infradead.org, Richard Henderson , jgross@suse.com, robin.murphy@arm.com, linux-kernel@vger.kernel.org, linux-alpha@vger.kernel.org, Borislav Petkov , linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Peter Zijlstra writes: > On Mon, Jan 07, 2019 at 04:27:27PM +0000, Andrew Murray wrote: >> For drivers that do not support context exclusion let's advertise the >> PERF_PMU_CAP_NOEXCLUDE capability. This ensures that perf will >> prevent us from handling events where any exclusion flags are set. >> Let's also remove the now unnecessary check for exclusion flags. >> >> Signed-off-by: Andrew Murray >> --- >> arch/x86/events/amd/ibs.c | 13 +------------ >> arch/x86/events/amd/power.c | 10 ++-------- >> arch/x86/events/intel/cstate.c | 12 +++--------- >> arch/x86/events/intel/rapl.c | 9 ++------- >> arch/x86/events/intel/uncore_snb.c | 9 ++------- >> arch/x86/events/msr.c | 10 ++-------- >> 6 files changed, 12 insertions(+), 51 deletions(-) > > You (correctly) don't add CAP_NO_EXCLUDE to the main x86 pmu code, but > then you also don't check if it handles all the various exclude options > correctly/consistently. > > Now; I must admit that that is a bit of a maze, but I think we can at > least add exclude_idle and exclude_hv fails in there, nothing uses those > afaict. > > On the various exclude options; they are as follows (IIUC): > > - exclude_guest: we're a HV/host-kernel and we don't want the counter > to run when we run a guest context. > > - exclude_host: we're a HV/host-kernel and we don't want the counter > to run when we run in host context. > > - exclude_hv: we're a guest and don't want the counter to run in HV > context. > > Now, KVM always implies exclude_hv afaict (for guests) On Power it mostly does. There's some host code that can run in real mode (MMU off) and therefore doesn't do a full context switch out of the guest (including the PMU), so that's host code that is running while the guest PMCs are still counting. cheers