From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
To: Alexander Graf <agraf@suse.de>,
benh@kernel.crashing.org, paulus@samba.org
Cc: linuxppc-dev@lists.ozlabs.org, kvm@vger.kernel.org,
kvm-ppc@vger.kernel.org
Subject: Re: [PATCH 1/4] KVM: PPC: BOOK3S: PR: Emulate virtual timebase register
Date: Thu, 05 Jun 2014 23:03:15 +0530 [thread overview]
Message-ID: <87sinjqn1g.fsf@linux.vnet.ibm.com> (raw)
In-Reply-To: <5390A071.9040006@suse.de>
Alexander Graf <agraf@suse.de> writes:
> On 05.06.14 17:50, Aneesh Kumar K.V wrote:
>> Alexander Graf <agraf@suse.de> writes:
>>
>>> On 05.06.14 14:08, Aneesh Kumar K.V wrote:
>>>> virtual time base register is a per VM, per cpu register that needs
>>>> to be saved and restored on vm exit and entry. Writing to VTB is not
>>>> allowed in the privileged mode.
>>>>
>>>> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
.......
>>>> break;
>>>> diff --git a/arch/powerpc/kvm/book3s_emulate.c b/arch/powerpc/kvm/book3s_emulate.c
>>>> index 3565e775b61b..1bb16a59dcbc 100644
>>>> --- a/arch/powerpc/kvm/book3s_emulate.c
>>>> +++ b/arch/powerpc/kvm/book3s_emulate.c
>>>> @@ -577,6 +577,9 @@ int kvmppc_core_emulate_mfspr_pr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val
>>>> */
>>>> *spr_val = vcpu->arch.spurr;
>>>> break;
>>>> + case SPRN_VTB:
>>>> + *spr_val = vcpu->arch.vtb;
>>> Doesn't this mean that vtb can be the same 2 when the guest reads it 2
>>> times in a row without getting preempted?
>>
>> But a mfspr will result in VM exit and that would make sure we
>> update vcpu->arch.vtb with the correct value.
>
> We only call kvmppc_core_vcpu_put_pr() when we context switch away from
> KVM, so it won't be updated, no?
>
>
kvmppc_copy_from_svcpu is also called from VM exit path (book3s_interrupt.S)
-aneesh
next prev parent reply other threads:[~2014-06-05 17:33 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-05 12:08 KVM: PPC: BOOK3S: PR: P8 Support Aneesh Kumar K.V
2014-06-05 12:08 ` [PATCH 1/4] KVM: PPC: BOOK3S: PR: Emulate virtual timebase register Aneesh Kumar K.V
2014-06-05 12:19 ` Alexander Graf
2014-06-05 15:50 ` Aneesh Kumar K.V
2014-06-05 16:53 ` Alexander Graf
2014-06-05 17:33 ` Aneesh Kumar K.V [this message]
2014-06-05 22:32 ` Alexander Graf
2014-06-05 22:36 ` Alexander Graf
2014-06-06 10:44 ` Alexander Graf
2014-06-06 16:27 ` Aneesh Kumar K.V
2014-07-28 13:25 ` Alexander Graf
2014-07-28 22:59 ` Stewart Smith
2014-06-05 12:08 ` [PATCH 2/4] KVM: PPC: BOOK3S: PR: Doorbell support Aneesh Kumar K.V
2014-06-05 12:21 ` Alexander Graf
2014-06-05 12:23 ` Alexander Graf
2014-06-05 15:55 ` Aneesh Kumar K.V
2014-06-06 9:28 ` Aneesh Kumar K.V
2014-06-05 12:08 ` [PATCH 3/4] KVM: PPC: BOOK3S: PR: Emulate DPDES register Aneesh Kumar K.V
2014-06-05 12:08 ` [PATCH 4/4] KVM: PPC: BOOK3S: PR: Emulate instruction counter Aneesh Kumar K.V
2014-06-06 10:24 ` KVM: PPC: BOOK3S: PR: P8 Support Alexander Graf
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