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Thu, 2 Jul 2020 06:22:42 +0000 (GMT) Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6730F4C04A; Thu, 2 Jul 2020 06:22:40 +0000 (GMT) Received: from [9.85.81.233] (unknown [9.85.81.233]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTPS; Thu, 2 Jul 2020 06:22:40 +0000 (GMT) From: Athira Rajeev Message-Id: <9692404F-A567-479B-BF9B-3624E71639FB@linux.vnet.ibm.com> Content-Type: multipart/alternative; boundary="Apple-Mail=_CD3873F7-2EA2-4365-9C84-3F96807D1A85" Mime-Version: 1.0 (Mac OS X Mail 13.4 \(3608.80.23.2.2\)) Subject: Re: [PATCH v2 02/10] KVM: PPC: Book3S HV: Save/restore new PMU registers Date: Thu, 2 Jul 2020 11:52:37 +0530 In-Reply-To: <20200701111158.GA694641@thinks.paulus.ozlabs.org> To: Paul Mackerras References: <1593595262-1433-1-git-send-email-atrajeev@linux.vnet.ibm.com> <1593595262-1433-3-git-send-email-atrajeev@linux.vnet.ibm.com> <20200701111158.GA694641@thinks.paulus.ozlabs.org> X-Mailer: Apple Mail (2.3608.80.23.2.2) X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-07-02_02:2020-07-01, 2020-07-02 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 adultscore=0 mlxlogscore=999 lowpriorityscore=0 cotscore=-2147483648 impostorscore=0 suspectscore=0 phishscore=0 mlxscore=0 clxscore=1011 malwarescore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2004280000 definitions=main-2007020046 X-Mailman-Approved-At: Thu, 02 Jul 2020 16:30:48 +1000 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mikey@neuling.org, maddy@linux.vnet.ibm.com, linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" --Apple-Mail=_CD3873F7-2EA2-4365-9C84-3F96807D1A85 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=us-ascii > On 01-Jul-2020, at 4:41 PM, Paul Mackerras wrote: >=20 > On Wed, Jul 01, 2020 at 05:20:54AM -0400, Athira Rajeev wrote: >> PowerISA v3.1 has added new performance monitoring unit (PMU) >> special purpose registers (SPRs). They are >>=20 >> Monitor Mode Control Register 3 (MMCR3) >> Sampled Instruction Event Register A (SIER2) >> Sampled Instruction Event Register B (SIER3) >>=20 >> Patch addes support to save/restore these new >> SPRs while entering/exiting guest. >=20 > This mostly looks reasonable, at a quick glance at least, but I am > puzzled by two of the changes you are making. See below. >=20 >> diff --git a/arch/powerpc/kvm/book3s_hv.c = b/arch/powerpc/kvm/book3s_hv.c >> index 6bf66649..c265800 100644 >> --- a/arch/powerpc/kvm/book3s_hv.c >> +++ b/arch/powerpc/kvm/book3s_hv.c >> @@ -1698,7 +1698,8 @@ static int kvmppc_get_one_reg_hv(struct = kvm_vcpu *vcpu, u64 id, >> *val =3D get_reg_val(id, vcpu->arch.sdar); >> break; >> case KVM_REG_PPC_SIER: >> - *val =3D get_reg_val(id, vcpu->arch.sier); >> + i =3D id - KVM_REG_PPC_SIER; >> + *val =3D get_reg_val(id, vcpu->arch.sier[i]); >=20 > This is inside a switch (id) statement, so here we know that id is > KVM_REG_PPC_SIER. In other words i will always be zero, so what is > the point of doing the subtraction? >=20 >> break; >> case KVM_REG_PPC_IAMR: >> *val =3D get_reg_val(id, vcpu->arch.iamr); >> @@ -1919,7 +1920,8 @@ static int kvmppc_set_one_reg_hv(struct = kvm_vcpu *vcpu, u64 id, >> vcpu->arch.sdar =3D set_reg_val(id, *val); >> break; >> case KVM_REG_PPC_SIER: >> - vcpu->arch.sier =3D set_reg_val(id, *val); >> + i =3D id - KVM_REG_PPC_SIER; >> + vcpu->arch.sier[i] =3D set_reg_val(id, *val); >=20 > Same comment here. Hi Paul, Thanks for reviewing the patch. Yes, true that currently `id` will be = zero since it is only KVM_REG_PPC_SIER. I have kept the subtraction here = considering that there will be addition of new registers to switch case.=20= ex: case KVM_REG_PPC_SIER..KVM_REG_PPC_SIER3 >=20 > I think that new defines for the new registers will need to be added > to arch/powerpc/include/uapi/asm/kvm.h and > Documentation/virt/kvm/api.rst, and then new cases will need to be > added to these switch statements. Yes, New registers are not yet added to kvm.h=20 I will address these comments and include changes for = arch/powerpc/include/uapi/asm/kvm.h and Documentation/virt/kvm/api.rst = in the next version. >=20 > By the way, please cc kvm-ppc@vger.kernel.org and kvm@vger.kernel.org > on KVM patches. Sure, will include KVM mailing list in the next version Thanks Athira=20 >=20 > Paul. --Apple-Mail=_CD3873F7-2EA2-4365-9C84-3F96807D1A85 Content-Transfer-Encoding: quoted-printable Content-Type: text/html; charset=us-ascii

On 01-Jul-2020, at 4:41 PM, Paul Mackerras <paulus@ozlabs.org> = wrote:

On Wed, Jul 01, 2020 at 05:20:54AM -0400, Athira Rajeev = wrote:
PowerISA v3.1 = has added new performance monitoring unit (PMU)
special = purpose registers (SPRs). They are

Monitor = Mode Control Register 3 (MMCR3)
Sampled Instruction Event = Register A (SIER2)
Sampled Instruction Event Register B = (SIER3)

Patch addes support to save/restore = these new
SPRs while entering/exiting guest.

This mostly looks reasonable, at = a quick glance at least, but I am
puzzled by two of the = changes you are making.  See below.

diff --git = a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index 6bf66649..c265800 100644
--- = a/arch/powerpc/kvm/book3s_hv.c
+++ = b/arch/powerpc/kvm/book3s_hv.c
@@ -1698,7 +1698,8 @@ = static int kvmppc_get_one_reg_hv(struct kvm_vcpu *vcpu, u64 id,
= = *val =3D get_reg_val(id, vcpu->arch.sdar);
= = = break;
case KVM_REG_PPC_SIER:
- = = *val =3D get_reg_val(id, vcpu->arch.sier);
+ i =3D id = - KVM_REG_PPC_SIER;
+ *val =3D get_reg_val(id, = vcpu->arch.sier[i]);

This = is inside a switch (id) statement, so here we know that id is
KVM_REG_PPC_SIER.  In other words i will always be zero, = so what is
the point of doing the subtraction?

break;
= case KVM_REG_PPC_IAMR:
*val =3D = get_reg_val(id, vcpu->arch.iamr);
@@ -1919,7 +1920,8 @@ = static int kvmppc_set_one_reg_hv(struct kvm_vcpu *vcpu, u64 id,
= = vcpu->arch.sdar =3D set_reg_val(id, *val);
= = = break;
case KVM_REG_PPC_SIER:
- = = vcpu->arch.sier =3D set_reg_val(id, *val);
+ i =3D id = - KVM_REG_PPC_SIER;
+ vcpu->arch.sier[i] =3D = set_reg_val(id, *val);

Same = comment here.

Hi Paul,

Thanks for reviewing the patch. = Yes, true that currently `id` will be zero since it is only = KVM_REG_PPC_SIER. I have kept the subtraction here considering that = there will be addition of new registers to switch case. 
ex: case = KVM_REG_PPC_SIER..KVM_REG_PPC_SIER3


I think that = new defines for the new registers will need to be added
to = arch/powerpc/include/uapi/asm/kvm.h and
Documentation/virt/kvm/api.rst, and then new cases will need = to be
added to these switch statements.

Yes, New registers = are not yet added to kvm.h 
I will address these comments and include = changes for arch/powerpc/include/uapi/asm/kvm.h and = Documentation/virt/kvm/api.rst in the
next version.


By the way, = please cc kvm-ppc@vger.kernel.org and kvm@vger.kernel.org
on KVM patches.
Sure, = will include KVM mailing list in the next version

Thanks
Athira 

Paul.

= --Apple-Mail=_CD3873F7-2EA2-4365-9C84-3F96807D1A85--