From: "David Laight" <David.Laight@ACULAB.COM>
To: "Eric B Munson" <emunson@mgebm.net>
Cc: a.p.zijlstra@chello.nl, linux-kernel@vger.kernel.org,
paulus@samba.org, anton@samba.org, acme@ghostprotocols.net,
mingo@elte.hu, linuxppc-dev@lists.ozlabs.org, stable@kernel.org
Subject: RE: [PATCH V4] POWER: perf_event: Skip updating kernel counters if register value shrinks
Date: Wed, 27 Apr 2011 14:13:25 +0100 [thread overview]
Message-ID: <AE90C24D6B3A694183C094C60CF0A2F6D8AD06@saturn3.aculab.com> (raw)
In-Reply-To: <20110427130822.GC2936@mgebm.net>
=20
> prev and val are both 64 bit variables holding 32 bit numbers, we do
not
> accumulate in either, they are both replaced by values directly from
the
> registers.
> So prev > val will not always be true.
The code seems to be:
prev =3D local64_read(&event->hw.prev_count);
val =3D read_pmc(event->hw.idx);
delta =3D check_and_compute_delta(prev, val);
local64_add(delta, &event->count);
Which looks very much like 'prev' being a 64bit counter generated
from the 32bit pmc register.
David
next prev parent reply other threads:[~2011-04-27 13:14 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-04-15 18:12 [PATCH V4] POWER: perf_event: Skip updating kernel counters if register value shrinks Eric B Munson
2011-04-27 7:40 ` David Laight
2011-04-27 12:19 ` Eric B Munson
2011-04-27 12:34 ` David Laight
2011-04-27 12:59 ` Eric B Munson
2011-04-27 13:04 ` David Laight
2011-04-27 12:42 ` David Laight
2011-04-27 13:08 ` Eric B Munson
2011-04-27 13:13 ` David Laight [this message]
2011-04-27 13:20 ` Eric B Munson
2011-04-27 13:26 ` Benjamin Herrenschmidt
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