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In-Reply-To: <1595489557-2047-1-git-send-email-atrajeev@linux.vnet.ibm.com>
From: Jordan Niethe <jniethe5@gmail.com>
Date: Thu, 23 Jul 2020 17:40:26 +1000
Message-ID: <CACzsE9ogrEtmD9=fDZ0vMdFL7Tgo=132wdEb9mHbjoueRLj-dg@mail.gmail.com>
Subject: Re: [v4] powerpc/perf: Initialize power10 PMU registers in cpu setup
 routine
To: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
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On Thu, Jul 23, 2020 at 5:32 PM Athira Rajeev
<atrajeev@linux.vnet.ibm.com> wrote:
>
> Initialize Monitor Mode Control Register 3 (MMCR3)
> SPR which is new in power10. For PowerISA v3.1, BHRB disable
> is controlled via Monitor Mode Control Register A (MMCRA) bit,
> namely "BHRB Recording Disable (BHRBRD)". This patch also initializes
> MMCRA BHRBRD to disable BHRB feature at boot for power10.
>
> Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Reviewed-by: Jordan Niethe <jniethe5@gmail.com>
> ---
> Dependency:
> - On power10 PMU base enablement series V3:
>   https://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=190462
>
> Changes from v3 -> v4
> - Addressed review comments from Jordan and Michael Ellerman.
>   This patch was initially part of Power10 PMU base enablement
>   series. Moving this as separate patch as suggested by Michael
>   Ellerman. Hence dependency of initial series Patch 7 which defines
>   MMCRA_BHRB_DISABLE. Addressed review comments from Jordan to make
>   sure existing PMU function (__INIT_PMU) will not overwrite ISA 3.1
>   updates
>
> Changes from v2 -> v3
> - Addressed review comment from Michael Ellerman to
>   call PMU init from __setup_cpu_power10
>
>  arch/powerpc/kernel/cpu_setup_power.S | 19 +++++++++++++++----
>  1 file changed, 15 insertions(+), 4 deletions(-)
>
> diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S
> index efdcfa7..3fa6eef 100644
> --- a/arch/powerpc/kernel/cpu_setup_power.S
> +++ b/arch/powerpc/kernel/cpu_setup_power.S
> @@ -94,13 +94,15 @@ _GLOBAL(__restore_cpu_power8)
>  _GLOBAL(__setup_cpu_power10)
>         mflr    r11
>         bl      __init_FSCR_power10
> +       bl      __init_PMU
> +       bl      __init_PMU_ISA31
>         b       1f
>
>  _GLOBAL(__setup_cpu_power9)
>         mflr    r11
>         bl      __init_FSCR
> -1:     bl      __init_PMU
> -       bl      __init_hvmode_206
> +       bl      __init_PMU
> +1:     bl      __init_hvmode_206
>         mtlr    r11
>         beqlr
>         li      r0,0
> @@ -124,13 +126,15 @@ _GLOBAL(__setup_cpu_power9)
>  _GLOBAL(__restore_cpu_power10)
>         mflr    r11
>         bl      __init_FSCR_power10
> +       bl      __init_PMU
> +       bl      __init_PMU_ISA31
>         b       1f
>
>  _GLOBAL(__restore_cpu_power9)
>         mflr    r11
>         bl      __init_FSCR
> -1:     bl      __init_PMU
> -       mfmsr   r3
> +       bl      __init_PMU
> +1:     mfmsr   r3
>         rldicl. r0,r3,4,63
>         mtlr    r11
>         beqlr
> @@ -233,3 +237,10 @@ __init_PMU_ISA207:
>         li      r5,0
>         mtspr   SPRN_MMCRS,r5
>         blr
> +
> +__init_PMU_ISA31:
> +       li      r5,0
> +       mtspr   SPRN_MMCR3,r5
> +       LOAD_REG_IMMEDIATE(r5, MMCRA_BHRB_DISABLE)
> +       mtspr   SPRN_MMCRA,r5
> +       blr
> --
> 1.8.3.1
>