Patch for '5.3.7 64-bits kernel doesn't boot on G5 Quad' found (was: Re: PPC64: G5 & 4k/64k page size)

From: Romain Dolbeau <romain@dolbeau.org>
To: Bertrand <bertrand.dekoninck@gmail.com>
Cc: "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com>,
	Jeroen Diederen <jjhdiederen@zonnet.nl>,
	PowerPC List Debian <debian-powerpc@lists.debian.org>,
	Andreas Schwab <schwab@linux-m68k.org>,
	John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>,
	linuxppc-dev@lists.ozlabs.org
Subject: Patch for '5.3.7 64-bits kernel doesn't boot on G5 Quad' found (was: Re: PPC64: G5 & 4k/64k page size)
Date: Tue, 7 Jan 2020 19:34:22 +0100	[thread overview]
Message-ID: <CADuzgboztYeRbruGmQDuTScaLAZp2ozoy-KARtNq1ViyTm86jw@mail.gmail.com> (raw)
In-Reply-To: <113ee36c-684f-9201-aea8-8cd437b6d009@gmail.com>

[-- Attachment #1: Type: text/plain, Size: 674 bytes --]

Hello all,

Great news: Aneesh sent me a patch that solves the problem on my G5 Quad :-)

I don't know whether he considers it a 'workaround' or if it's the
'proper' patch for upstream, so beware. It's a one-liner so I attach
it to this message: those affected can test it as well to confirm if
that indeed solves the problem for them as well.

If it is the 'proper' patch, I expect it should get into upstream
pretty quickly. Then Debian should be able to trivially backport it to
their PPC64 kernel, and the G5 will still be a great machine in 2020!

Thanks everyone for your help in tracking down the bug & to Aneesh for
finding a fix :-)

Cordially,

-- 
Romain Dolbeau

[-- Attachment #2: g5.patch --]
[-- Type: text/x-patch, Size: 617 bytes --]

diff --git a/arch/powerpc/include/asm/book3s/64/mmu-hash.h b/arch/powerpc/include/asm/book3s/64/mmu-hash.h
index 15b75005bc34..516db8a2e6ca 100644
--- a/arch/powerpc/include/asm/book3s/64/mmu-hash.h
+++ b/arch/powerpc/include/asm/book3s/64/mmu-hash.h
@@ -601,7 +601,7 @@ extern void slb_set_size(u16 size);
  */
 #define MAX_USER_CONTEXT	((ASM_CONST(1) << CONTEXT_BITS) - 2)
 #define MIN_USER_CONTEXT	(MAX_KERNEL_CTX_CNT + MAX_VMALLOC_CTX_CNT + \
-				 MAX_IO_CTX_CNT + MAX_VMEMMAP_CTX_CNT)
+				 MAX_IO_CTX_CNT + MAX_VMEMMAP_CTX_CNT + 1)
 /*
  * For platforms that support on 65bit VA we limit the context bits
  */
