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[209.85.167.42]) by smtp.gmail.com with ESMTPSA id y26sm567305ljm.132.2020.07.28.12.02.25 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 28 Jul 2020 12:02:25 -0700 (PDT) Received: by mail-lf1-f42.google.com with SMTP id s9so11619145lfs.4 for ; Tue, 28 Jul 2020 12:02:25 -0700 (PDT) X-Received: by 2002:a05:6512:2082:: with SMTP id t2mr15641334lfr.142.1595962944925; Tue, 28 Jul 2020 12:02:24 -0700 (PDT) MIME-Version: 1.0 References: <20200723211432.b31831a0df3bc2cbdae31b40@linux-foundation.org> <20200724041508.QlTbrHnfh%akpm@linux-foundation.org> <0323de82-cfbd-8506-fa9c-a702703dd654@linux.alibaba.com> <20200727110512.GB25400@gaia> <39560818-463f-da3a-fc9e-3a4a0a082f61@linux.alibaba.com> <1595932767.wga6c4yy6a.astroid@bobo.none> In-Reply-To: <1595932767.wga6c4yy6a.astroid@bobo.none> From: Linus Torvalds Date: Tue, 28 Jul 2020 12:02:08 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [patch 01/15] mm/memory.c: avoid access flag update TLB flush for retried page fault To: Nicholas Piggin Content-Type: text/plain; charset="UTF-8" X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arch , Hillf Danton , Yang Shi , Yu Xu , Catalin Marinas , Hugh Dickins , Josef Bacik , Will Deacon , Linux-MM , Matthew Wilcox , Johannes Weiner , mm-commits@vger.kernel.org, Andrew Morton , linuxppc-dev , "Kirill A . Shutemov" Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Tue, Jul 28, 2020 at 3:53 AM Nicholas Piggin wrote: > > The quirk is a problem with coprocessor where it's supposed to > invalidate the translation after a fault but it doesn't, so we can get a > read-only TLB stuck after something else does a RO->RW upgrade on the > TLB. Something like that IIRC. Coprocessors have their own MMU which > lives in the nest not the core, so you need a global TLB flush to > invalidate that thing. So I assumed, but it does seem confused. Why? Because if there are stale translations on the co-processor, there's no guarantee that one of the CPU's will have them and take a fault. So I'm not seeing why a core CPU doing spurious TLB invalidation would follow from "stale TLB in the Nest". If anything, I think "we have a coprocessor that needs to never have stale TLB entries" would impact the _regular_ TLB invalidates (by update_mmu_cache()) and perhaps make those more aggressive, exactly because the coprocessor may not handle the fault as gracefully. I dunno. I don't know the coprocessor side well enough to judge, I'm just looking at it from a conceptual standpoint. Linus