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From: Arnd Bergmann <arnd@arndb.de>
Date: Fri, 17 May 2019 10:58:37 +0200
Message-ID: <CAK8P3a0kKb7njiJvUkwJYwf-yc-hEyErSiWcvbdf0XnMoctzrg@mail.gmail.com>
Subject: Re: [EXT] Re: [PATCH 2/3] arm64: dts: ls1028a: Add PCIe controller DT
 nodes
To: Xiaowei Bao <xiaowei.bao@nxp.com>
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On Fri, May 17, 2019 at 5:21 AM Xiaowei Bao <xiaowei.bao@nxp.com> wrote:
> -----Original Message-----
> From: Arnd Bergmann <arnd@arndb.de>
> On Wed, May 15, 2019 at 9:36 AM Xiaowei Bao <xiaowei.bao@nxp.com> wrote:
> > Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> > ---
> >  arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi |   52 ++++++++++++++++=
++++++++
> >  1 files changed, 52 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm6=
4/boot/dts/freescale/fsl-ls1028a.dtsi
> > index b045812..50b579b 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > @@ -398,6 +398,58 @@
> >                         status =3D "disabled";
> >                 };
> >
> > +               pcie@3400000 {
> > +                       compatible =3D "fsl,ls1028a-pcie";
> > +                       reg =3D <0x00 0x03400000 0x0 0x00100000   /* co=
ntroller registers */
> > +                              0x80 0x00000000 0x0 0x00002000>; /* conf=
iguration space */
> > +                       reg-names =3D "regs", "config";
> > +                       interrupts =3D <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH=
>, /* PME interrupt */
> > +                                    <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;=
 /* aer interrupt */
> > +                       interrupt-names =3D "pme", "aer";
> > +                       #address-cells =3D <3>;
> > +                       #size-cells =3D <2>;
> > +                       device_type =3D "pci";
> > +                       dma-coherent;
> > +                       num-lanes =3D <4>;
> > +                       bus-range =3D <0x0 0xff>;
> > +                       ranges =3D <0x81000000 0x0 0x00000000 0x80 0x00=
010000 0x0 0x00010000   /* downstream I/O */
> > +                                 0x82000000 0x0 0x40000000 0x80 0x4000=
0000 0x0 0x40000000>; /* non-prefetchable memory */
>
> Are you sure there is no support for 64-bit BARs or prefetchable memory?
> [Xiaowei Bao] sorry for late reply, Thought that our Layerscape platform =
has not added prefetchable memory support in DTS, so this platform has not =
been added, I will submit a separate patch to add prefetchable memory suppo=
rt for all Layerscape platforms.

Ok, thanks.

> Of course, the prefetchable PCIE device can work in our boards, because t=
he RC will
> assign non-prefetchable memory for this device. We reserve 1G no-prefetch=
able
> memory for PCIE device, it is enough for general devices.

Sure, many devices work just fine, this is mostly a question of supporting =
those
devices that do require multiple gigabytes, or that need prefetchable memor=
y
semantics to get the expected performance. GPUs are the obvious example,
but I think there are others (infiniband?).

      Arnd