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[203.221.202.134]) by smtp.gmail.com with ESMTPSA id c27-20020aa7953b000000b0056c04dee930sm6022098pfp.120.2022.11.08.02.09.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 08 Nov 2022 02:09:48 -0800 (PST) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Tue, 08 Nov 2022 20:09:44 +1000 Message-Id: Subject: Re: [PATCH v2 1/4] powerpc/64: Add INTERRUPT_SANITIZE_REGISTERS Kconfig From: "Nicholas Piggin" To: "Segher Boessenkool" , "Rohan McLure" X-Mailer: aerc 0.11.0 References: <20221107033202.1375238-1-rmclure@linux.ibm.com> <20221107163923.GO25951@gate.crashing.org> In-Reply-To: <20221107163923.GO25951@gate.crashing.org> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Tue Nov 8, 2022 at 2:39 AM AEST, Segher Boessenkool wrote: > Hi! > > On Mon, Nov 07, 2022 at 02:31:59PM +1100, Rohan McLure wrote: > > Add Kconfig option for enabling clearing of registers on arrival in an > > interrupt handler. This reduces the speculation influence of registers > > on kernel internals. > > Assuming you are talking about existing PowerPC CPUs from the last 30 > years: > > There is no data speculation. At all. Ever. > > There is branch prediction, but that is not influenced by register > contents, either (for any current CPUs at least). (Except when you get > a flush because of a mispredict, but if this zeroing changes anything, > we will have used wild (but user controlled) values in the old > non-zeroing situation, and that is a much bigger problem itself already, > also for security! This can be an unlikely kernel bug, or a very > unlikely compiler bug.) This is not about data speculation, it is about speculative execution in kernel mode that uses architected value that were set by user, and that value being used to influence a speculative gadget that can expose data to user via a side channel. > All GPRs are renamed, always. If you zero all GPRs on interrupt entry > (which is context synchronising, importantly), this will guarantee there > can be no timing influence from the GPRs, because all of the physical > registers depend on nothing that happened before. So that is good, at > least it can give some peace of mind. Except that this makes 30 new > registers in just a few cycles, which *itself* can cause stalls, if the > renaming things are still busy. It will have some pipeline effect like any instruction I suppose. At least in latest processors, zeroing idiom should release registers AFAIK. > Context synchronising does not > necessarily help there, the renaming machinery can do stuff *after* an > insn completes. Possibly context synchronization does not push everything prior to completion, certainly it does not drain prior stores from store queues even if they had previously completed, so there can be things going on there. Software does not really have the ability to do anything about that though, so that's more of a hardware problem if that exposes a security issue IMO. Or at least a separate issue if there is some architecture that could deal with it. Thanks, Nick