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[193.116.112.94]) by smtp.gmail.com with ESMTPSA id d13-20020a63fd0d000000b00477def759cbsm6848584pgh.58.2022.11.29.01.48.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 29 Nov 2022 01:48:38 -0800 (PST) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Tue, 29 Nov 2022 19:48:34 +1000 Message-Id: Subject: Re: [PATCH v4 4/7] powerpc/64s: IOption for MSR stored in r12 From: "Nicholas Piggin" To: "Rohan McLure" , X-Mailer: aerc 0.13.0 References: <20221129044354.1836018-1-rmclure@linux.ibm.com> <20221129044354.1836018-4-rmclure@linux.ibm.com> In-Reply-To: <20221129044354.1836018-4-rmclure@linux.ibm.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Tue Nov 29, 2022 at 2:43 PM AEST, Rohan McLure wrote: > Interrupt handlers in asm/exceptions-64s.S contain a great deal of common > code produced by the GEN_COMMON macros. Currently, at the exit point of > the macro, r12 will contain the contents of the MSR. A future patch will > cause these macros to zeroise architected registers to avoid potential > speculation influence of user data. > > Provide an IOption that signals that r12 must be retained, as the > interrupt handler assumes it to hold the contents of the MSR. Reviewed-by: Nicholas Piggin > > Signed-off-by: Rohan McLure > --- > v4: Split 64s register sanitisation commit to establish this IOption > --- > arch/powerpc/kernel/exceptions-64s.S | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/e= xceptions-64s.S > index 5381a43e50fe..58d72db1d484 100644 > --- a/arch/powerpc/kernel/exceptions-64s.S > +++ b/arch/powerpc/kernel/exceptions-64s.S > @@ -111,6 +111,7 @@ name: > #define ISTACK .L_ISTACK_\name\() /* Set regular kernel stack */ > #define __ISTACK(name) .L_ISTACK_ ## name > #define IKUAP .L_IKUAP_\name\() /* Do KUAP lock */ > +#define IMSR_R12 .L_IMSR_R12_\name\() /* Assumes MSR saved to r12 */ > =20 > #define INT_DEFINE_BEGIN(n) \ > .macro int_define_ ## n name > @@ -176,6 +177,9 @@ do_define_int n > .ifndef IKUAP > IKUAP=3D1 > .endif > + .ifndef IMSR_R12 > + IMSR_R12=3D0 > + .endif > .endm > =20 > /* > @@ -1751,6 +1755,7 @@ INT_DEFINE_BEGIN(fp_unavailable) > #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE > IKVM_REAL=3D1 > #endif > + IMSR_R12=3D1 > INT_DEFINE_END(fp_unavailable) > =20 > EXC_REAL_BEGIN(fp_unavailable, 0x800, 0x100) > @@ -2372,6 +2377,7 @@ INT_DEFINE_BEGIN(altivec_unavailable) > #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE > IKVM_REAL=3D1 > #endif > + IMSR_R12=3D1 > INT_DEFINE_END(altivec_unavailable) > =20 > EXC_REAL_BEGIN(altivec_unavailable, 0xf20, 0x20) > @@ -2421,6 +2427,7 @@ INT_DEFINE_BEGIN(vsx_unavailable) > #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE > IKVM_REAL=3D1 > #endif > + IMSR_R12=3D1 > INT_DEFINE_END(vsx_unavailable) > =20 > EXC_REAL_BEGIN(vsx_unavailable, 0xf40, 0x20) > --=20 > 2.37.2