From: "S.j. Wang" <shengjiu.wang@nxp.com>
To: Nicolin Chen <nicoleotsuka@gmail.com>
Cc: "alsa-devel@alsa-project.org" <alsa-devel@alsa-project.org>,
"timur@kernel.org" <timur@kernel.org>,
"Xiubo.Lee@gmail.com" <Xiubo.Lee@gmail.com>,
"festevam@gmail.com" <festevam@gmail.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"broonie@kernel.org" <broonie@kernel.org>,
"linuxppc-dev@lists.ozlabs.org" <linuxppc-dev@lists.ozlabs.org>
Subject: Re: [PATCH] ASoC: fsl_esai: fix the channel swap issue after xrun
Date: Thu, 23 May 2019 09:53:42 +0000 [thread overview]
Message-ID: <VE1PR04MB647934199C3AA60759BED888E3010@VE1PR04MB6479.eurprd04.prod.outlook.com> (raw)
Hi
> > + /*
> > + * Add fifo reset here, because the regcache_sync will
> > + * write one more data to ETDR.
> > + * Which will cause channel shift.
>
> Sounds like a bug to me...should fix it first by marking the data registers as
> volatile.
>
The ETDR is a writable register, it is not volatile. Even we change it to
Volatile, I don't think we can't avoid this issue. for the regcache_sync
Just to write this register, it is correct behavior.
Best regards
Wang shengjiu
next reply other threads:[~2019-05-23 9:55 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-23 9:53 S.j. Wang [this message]
2019-05-23 10:10 ` [PATCH] ASoC: fsl_esai: fix the channel swap issue after xrun Nicolin Chen
-- strict thread matches above, loose matches on Subject: below --
2019-06-05 10:29 S.j. Wang
2019-06-06 0:16 ` Nicolin Chen
2019-05-23 11:04 S.j. Wang
2019-05-23 22:50 ` Nicolin Chen
2019-05-17 3:09 S.j. Wang
2019-05-17 20:01 ` Nicolin Chen
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