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From: Mark Brown <broonie@kernel.org>
To: Shengjiu Wang <shengjiu.wang@nxp.com>
Cc: devicetree@vger.kernel.org, alsa-devel@alsa-project.org,
	linuxppc-dev@lists.ozlabs.org, Xiubo.Lee@gmail.com,
	festevam@gmail.com, tiwai@suse.com, lgirdwood@gmail.com,
	perex@perex.cz, nicoleotsuka@gmail.com, robh+dt@kernel.org,
	krzk+dt@kernel.org, shengjiu.wang@gmail.com,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 3/6] ASoC: fsl_micfil: Add support for PLL switch at runtime
Date: Thu, 30 Jun 2022 11:37:23 +0100	[thread overview]
Message-ID: <Yr1842e42P4piYnE@sirena.org.uk> (raw)
In-Reply-To: <1656567554-32122-4-git-send-email-shengjiu.wang@nxp.com>

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On Thu, Jun 30, 2022 at 01:39:11PM +0800, Shengjiu Wang wrote:

> +static int fsl_micfil_reparent_rootclk(struct fsl_micfil *micfil, unsigned int sample_rate)
> +{
> +	struct device *dev = &micfil->pdev->dev;
> +	u64 ratio = sample_rate;
> +	struct clk *clk;
> +	int ret;
> +
> +	/* Reparent clock if required condition is true */
> +	if (!micfil->pll8k_clk || !micfil->pll11k_clk)
> +		return 0;
> +
> +	ratio = do_div(ratio, 8000) ? CLK_11K_FREQ : CLK_8K_FREQ;
> +
> +	/* Get root clock */
> +	clk = micfil->mclk;
> +	if (IS_ERR_OR_NULL(clk)) {
> +		dev_err(dev, "no mclk clock in devicetree\n");
> +		return PTR_ERR(clk);
> +	}
> +
> +	/* Disable clock first, for it was enabled by pm_runtime */
> +	clk_disable_unprepare(clk);
> +	fsl_asoc_reparent_pll_clocks(dev, clk, micfil->pll8k_clk,
> +				     micfil->pll11k_clk, ratio);
> +	ret = clk_prepare_enable(clk);
> +	if (ret)
> +		return ret;
> +
> +	return 0;
> +}

Seems like more of this logic could be factored out into the reparent
function if the target sample rate is passed in?

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  reply	other threads:[~2022-06-30 10:38 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-30  5:39 [PATCH 0/6] Add support of two Audio PLL source Shengjiu Wang
2022-06-30  5:39 ` [PATCH 1/6] ASoC: fsl_utils: Add function to handle PLL clock source Shengjiu Wang
2022-06-30  5:39 ` [PATCH 2/6] ASoC: fsl_spdif: Add support for PLL switch at runtime Shengjiu Wang
2022-06-30  5:39 ` [PATCH 3/6] ASoC: fsl_micfil: " Shengjiu Wang
2022-06-30 10:37   ` Mark Brown [this message]
2022-06-30 12:15     ` Shengjiu Wang
2022-06-30  5:39 ` [PATCH 4/6] ASoC: fsl_sai: " Shengjiu Wang
2022-06-30  5:39 ` [PATCH 5/6] ASoC: dt-bindings: fsl_spdif: Add two PLL clock source Shengjiu Wang
2022-06-30  5:39 ` [PATCH 6/6] ASoC: dt-bindings: fsl-sai: " Shengjiu Wang

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