From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.0 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34F5DC432C3 for ; Tue, 3 Dec 2019 05:05:29 +0000 (UTC) Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8B17B206E0 for ; Tue, 3 Dec 2019 05:05:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=ozlabs-ru.20150623.gappssmtp.com header.i=@ozlabs-ru.20150623.gappssmtp.com header.b="fRZlsUEK" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8B17B206E0 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=ozlabs.ru Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 47RqgB1qFNzDqVQ for ; Tue, 3 Dec 2019 16:05:26 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=ozlabs.ru (client-ip=2607:f8b0:4864:20::1043; helo=mail-pj1-x1043.google.com; envelope-from=aik@ozlabs.ru; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=ozlabs.ru Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ozlabs-ru.20150623.gappssmtp.com header.i=@ozlabs-ru.20150623.gappssmtp.com header.b="fRZlsUEK"; dkim-atps=neutral Received: from mail-pj1-x1043.google.com (mail-pj1-x1043.google.com [IPv6:2607:f8b0:4864:20::1043]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 47RpmH27KWzDqRw for ; Tue, 3 Dec 2019 15:24:47 +1100 (AEDT) Received: by mail-pj1-x1043.google.com with SMTP id g4so958438pjs.10 for ; Mon, 02 Dec 2019 20:24:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ozlabs-ru.20150623.gappssmtp.com; s=20150623; h=subject:to:cc:references:from:autocrypt:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=+iD8qt10cwcl+Zcsb9BMw7NrGdk2excR5RtcTLqorng=; b=fRZlsUEKeesPhpBKwtBZ3hr6Eb3W7sHOi0Qp4DUzi/hnUk3HwLTAtWtYMjYCMfPcTu gXBPVFTqju6MwrkT9lB6XNgYoCoHYKtyzpmCbsnki+XlMkrd1hJJcCdjdIOk9FQHt9Xr vlYTtHN3fLQZYwpurHVbg6Rzo/dA7xmQ0p19sHFII7jDP0gEC4uWvg8ZyrLDVhtteDet SAitGE+Q7af2+IuluPuwIyoKJ6YJu0qc8qXiUwZcB9XC+eD8TXTuIhKphNENUo13trOu hxwyPSP+yLm1gsZo8Xu8A3QHxoD98KwE88mYy8Zrxro+txg1kRcM325+qU+0q508BQvA L/vQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:autocrypt :message-id:date:user-agent:mime-version:in-reply-to :content-language:content-transfer-encoding; bh=+iD8qt10cwcl+Zcsb9BMw7NrGdk2excR5RtcTLqorng=; b=sOtht240HT7ddBrV56k06EsjuL0YEuyGuhJ1ogKfDEtL3R82AMsEdpwo+8SrdY/J+2 9koEpQbxdqY/mko6nvtLG7P/J/TEV7cTtj+FRLUKROQgmZnGFsq/9rdBWduuc7YxraWJ cYV5A1goVngNr7kzsz7r6djQXdUvt4sJlr4jH9xSymaTweJRVHuzJrFJ/YbC/q0MwG1d CZkthY+OsYLWKS92qiR/lQihROYd5020M+NeQiN2u4lnupAutQrnLgyx2vevN4yHa2sD fWYohTFh1M6+8SiM4eB1SqQEkvQNIxP61PwQt03qm3TQxgalHOgBpQsUFVIvUaoCyI1Q YTUQ== X-Gm-Message-State: APjAAAV74UT2VGh2gX+nQtemO72+5rplZa+NEGz8QzT86WzD7skEzcqi Mev30Rnhwm0gQ4YFJpL45PyaNA== X-Google-Smtp-Source: APXvYqyQ9uGUgptAxHIcsMNtfijcK7Tl29cWW8S4VkvfWfDY3I9RkjgUHWpUi775jWhM2qvC7cP1iQ== X-Received: by 2002:a17:902:a714:: with SMTP id w20mr2908080plq.162.1575347085100; Mon, 02 Dec 2019 20:24:45 -0800 (PST) Received: from [10.61.2.175] ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id c1sm1227509pfa.51.2019.12.02.20.24.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 02 Dec 2019 20:24:44 -0800 (PST) Subject: Re: [PATCH v4 1/2] powerpc/pseries/iommu: Share the per-cpu TCE page with the hypervisor. To: Ram Pai References: <1575269124-17885-1-git-send-email-linuxram@us.ibm.com> <1575269124-17885-2-git-send-email-linuxram@us.ibm.com> <20191203020850.GA12354@oc0525413822.ibm.com> <0b56ce3e-6c32-5f3b-e7cc-0d419a61d71d@ozlabs.ru> <20191203040509.GB12354@oc0525413822.ibm.com> From: Alexey Kardashevskiy Autocrypt: addr=aik@ozlabs.ru; keydata= mQINBE+rT0sBEADFEI2UtPRsLLvnRf+tI9nA8T91+jDK3NLkqV+2DKHkTGPP5qzDZpRSH6mD EePO1JqpVuIow/wGud9xaPA5uvuVgRS1q7RU8otD+7VLDFzPRiRE4Jfr2CW89Ox6BF+q5ZPV /pS4v4G9eOrw1v09lEKHB9WtiBVhhxKK1LnUjPEH3ifkOkgW7jFfoYgTdtB3XaXVgYnNPDFo PTBYsJy+wr89XfyHr2Ev7BB3Xaf7qICXdBF8MEVY8t/UFsesg4wFWOuzCfqxFmKEaPDZlTuR tfLAeVpslNfWCi5ybPlowLx6KJqOsI9R2a9o4qRXWGP7IwiMRAC3iiPyk9cknt8ee6EUIxI6 t847eFaVKI/6WcxhszI0R6Cj+N4y+1rHfkGWYWupCiHwj9DjILW9iEAncVgQmkNPpUsZECLT WQzMuVSxjuXW4nJ6f4OFHqL2dU//qR+BM/eJ0TT3OnfLcPqfucGxubhT7n/CXUxEy+mvWwnm s9p4uqVpTfEuzQ0/bE6t7dZdPBua7eYox1AQnk8JQDwC3Rn9kZq2O7u5KuJP5MfludMmQevm pHYEMF4vZuIpWcOrrSctJfIIEyhDoDmR34bCXAZfNJ4p4H6TPqPh671uMQV82CfTxTrMhGFq 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Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: andmike@us.ibm.com, mst@redhat.com, mdroth@linux.vnet.ibm.com, linux-kernel@vger.kernel.org, ram.n.pai@gmail.com, cai@lca.pw, tglx@linutronix.de, sukadev@linux.vnet.ibm.com, linuxppc-dev@lists.ozlabs.org, hch@lst.de, bauerman@linux.ibm.com, david@gibson.dropbear.id.au Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On 03/12/2019 15:05, Ram Pai wrote: > On Tue, Dec 03, 2019 at 01:15:04PM +1100, Alexey Kardashevskiy wrote: >> >> >> On 03/12/2019 13:08, Ram Pai wrote: >>> On Tue, Dec 03, 2019 at 11:56:43AM +1100, Alexey Kardashevskiy wrote: >>>> >>>> >>>> On 02/12/2019 17:45, Ram Pai wrote: >>>>> H_PUT_TCE_INDIRECT hcall uses a page filled with TCE entries, as one of >>>>> its parameters. One page is dedicated per cpu, for the lifetime of the >>>>> kernel for this purpose. On secure VMs, contents of this page, when >>>>> accessed by the hypervisor, retrieves encrypted TCE entries. Hypervisor >>>>> needs to know the unencrypted entries, to update the TCE table >>>>> accordingly. There is nothing secret or sensitive about these entries. >>>>> Hence share the page with the hypervisor. >>>> >>>> This unsecures a page in the guest in a random place which creates an >>>> additional attack surface which is hard to exploit indeed but >>>> nevertheless it is there. >>>> A safer option would be not to use the >>>> hcall-multi-tce hyperrtas option (which translates FW_FEATURE_MULTITCE >>>> in the guest). >>> >>> >>> Hmm... How do we not use it? AFAICT hcall-multi-tce option gets invoked >>> automatically when IOMMU option is enabled. >> >> It is advertised by QEMU but the guest does not have to use it. > > Are you suggesting that even normal-guest, not use hcall-multi-tce? > or just secure-guest? Just secure. > >> >>> This happens even >>> on a normal VM when IOMMU is enabled. >>> >>> >>>> >>>> Also what is this for anyway? >>> >>> This is for sending indirect-TCE entries to the hypervisor. >>> The hypervisor must be able to read those TCE entries, so that it can >>> use those entires to populate the TCE table with the correct mappings. >>> >>>> if I understand things right, you cannot >>>> map any random guest memory, you should only be mapping that 64MB-ish >>>> bounce buffer array but 1) I do not see that happening (I may have >>>> missed it) 2) it should be done once and it takes a little time for >>>> whatever memory size we allow for bounce buffers anyway. Thanks, >>> >>> Any random guest memory can be shared by the guest. >> >> Yes but we do not want this to be this random. > > It is not sharing some random page. It is sharing a page that is > ear-marked for communicating TCE entries. Yes the address of the page > can be random, depending on where the allocator decides to allocate it. > The purpose of the page is not random. I was talking about the location. > That page is used for one specific purpose; to communicate the TCE > entries to the hypervisor. > >> I thought the whole idea >> of swiotlb was to restrict the amount of shared memory to bare minimum, >> what do I miss? > > I think, you are making a incorrect connection between this patch and > SWIOTLB. This patch has nothing to do with SWIOTLB. I can see this and this is the confusing part. >> >>> Maybe you are confusing this with the SWIOTLB bounce buffers used by >>> PCI devices, to transfer data to the hypervisor? >> >> Is not this for pci+swiotlb? > > > No. This patch is NOT for PCI+SWIOTLB. The SWIOTLB pages are a > different set of pages allocated and earmarked for bounce buffering. > > This patch is purely to help the hypervisor setup the TCE table, in the > presence of a IOMMU. Then the hypervisor should be able to access the guest pages mapped for DMA and these pages should be made unsecure for this to work. Where/when does this happen? >> The cover letter suggests it is for >> virtio-scsi-_pci_ with iommu_platform=on which makes it a >> normal pci device just like emulated XHCI. Thanks, > > Well, I guess, the cover letter is probably confusing. There are two > patches, which togather enable virtio on secure guests, in the presence > of IOMMU. > > The second patch enables virtio in the presence of a IOMMU, to use > DMA_ops+SWIOTLB infrastructure, to correctly navigate the I/O to virtio > devices. The second patch does nothing in relation to the problem being solved. > However that by itself wont work if the TCE entires are not correctly > setup in the TCE tables. The first patch; i.e this patch, helps > accomplish that. >> Hope this clears up the confusion. -- Alexey