From: Christophe Leroy <christophe.leroy@c-s.fr>
To: Benjamin Herrenschmidt <benh@kernel.crashing.org>,
Paul Mackerras <paulus@samba.org>,
Michael Ellerman <mpe@ellerman.id.au>,
Scott Wood <oss@buserror.net>
Cc: linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org
Subject: [PATCH 3/7] powerpc/32: Avoid risk of unrecoverable TLBmiss inside entry_32.S
Date: Wed, 12 Jul 2017 12:08:49 +0200 (CEST) [thread overview]
Message-ID: <e180ea05ab13a9e0099f09c2223aa509a2ba4329.1499633349.git.christophe.leroy@c-s.fr> (raw)
In-Reply-To: <cover.1499633349.git.christophe.leroy@c-s.fr>
By default, the 8xx pins an ITLB on the first 8M of memory in order
to avoid any ITLB miss on kernel code.
However, with some debug functions like DEBUG_PAGEALLOC and
DEBUG_RODATA, pinning TLBs is contradictory.
In order to avoid any ITLB miss in a critical section without pinning
TLBs, we have to ensure that there is no page boundary crossed between
the setup of a new value in SRR0/SRR1 and the associated RFI.
The functions modifying srr0/srr1 are all located in setup_32.S.
They are spread over almost 4kbytes.
The patch forces a 12 bits (4kbytes) alignment for those
functions. This garanties that the functions remain in a
single 4k page.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
arch/powerpc/kernel/entry_32.S | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
index 8587059ad848..4e9a359ceff6 100644
--- a/arch/powerpc/kernel/entry_32.S
+++ b/arch/powerpc/kernel/entry_32.S
@@ -43,6 +43,13 @@
#define LOAD_MSR_KERNEL(r, x) li r,(x)
#endif
+/*
+ * Align to 4k in order to ensure that all functions modyfing srr0/srr1
+ * fit into one page in order to not encounter a TLB miss between the
+ * modification of srr0/srr1 and the associated rfi.
+ */
+ .align 12
+
#ifdef CONFIG_BOOKE
.globl mcheck_transfer_to_handler
mcheck_transfer_to_handler:
--
2.12.0
next prev parent reply other threads:[~2017-07-12 10:08 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-07-12 10:08 [PATCH 0/7] Prepare 8xx for CONFIG_STRICT_KERNEL_RWX Christophe Leroy
2017-07-12 10:08 ` [PATCH 1/7] powerpc/8xx: Ensures RAM mapped with LTLB is seen as block mapped on 8xx Christophe Leroy
2017-08-16 12:29 ` [1/7] " Michael Ellerman
2017-07-12 10:08 ` [PATCH 2/7] powerpc/8xx: Remove macro that checks kernel address Christophe Leroy
2017-07-12 10:08 ` Christophe Leroy [this message]
2017-07-12 10:08 ` [PATCH 4/7] powerpc/8xx: Make pinning of ITLBs optional Christophe Leroy
2017-07-12 10:08 ` [PATCH 5/7] powerpc/8xx: Do not allow Pinned TLBs with STRICT_KERNEL_RWX or DEBUG_PAGEALLOC Christophe Leroy
2017-07-12 10:08 ` [PATCH 6/7] powerpc/8xx: mark init functions with __init Christophe Leroy
2017-07-12 10:08 ` [PATCH 7/7] powerpc/8xx: Reduce DTLB miss handler by one insn Christophe Leroy
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