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Thu, 21 May 2020 10:39:01 -0400 X-MC-Unique: PeNqcxDYOHKsxQkwu_xzYw-1 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 6A169106B244; Thu, 21 May 2020 14:39:00 +0000 (UTC) Received: from segfault.boston.devel.redhat.com (segfault.boston.devel.redhat.com [10.19.60.26]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 135CC12A4D; Thu, 21 May 2020 14:38:58 +0000 (UTC) From: Jeff Moyer To: "Aneesh Kumar K.V" , Dan Williams Subject: Re: [PATCH v2 3/5] libnvdimm/nvdimm/flush: Allow architecture to override the flush barrier References: <20200513034705.172983-1-aneesh.kumar@linux.ibm.com> <20200513034705.172983-3-aneesh.kumar@linux.ibm.com> <87v9kspk3x.fsf@linux.ibm.com> <87d070f2vs.fsf@linux.ibm.com> X-PGP-KeyID: 1F78E1B4 X-PGP-CertKey: F6FE 280D 8293 F72C 65FD 5A58 1FF8 A7CA 1F78 E1B4 Date: Thu, 21 May 2020 10:38:58 -0400 In-Reply-To: (Dan Williams's message of "Tue, 19 May 2020 11:59:30 -0700") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.1 (gnu/linux) MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair@popple.id.au, mpatocka@redhat.com, linuxppc-dev , linux-nvdimm Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Dan Williams writes: >> But I agree with your concern that if we have older kernel/applications >> that continue to use `dcbf` on future hardware we will end up >> having issues w.r.t powerfail consistency. The plan is what you outlined >> above as tighter ecosystem control. Considering we don't have a pmem >> device generally available, we get both kernel and userspace upgraded >> to use these new instructions before such a device is made available. I thought power already supported NVDIMM-N, no? So are you saying that those devices will continue to work with the existing flushing and fencing mechanisms? > Ok, I think a compile time kernel option with a runtime override > satisfies my concern. Does that work for you? The compile time option only helps when running newer kernels. I'm not sure how you would even begin to audit userspace applications (keep in mind, not every application is open source, and not every application uses pmdk). I also question the merits of forcing the administrator to make the determination of whether all applications on the system will work properly. Really, you have to rely on the vendor to tell you the platform is supported, and at that point, why put further hurdles in the way? The decision to require different instructions on ppc is unfortunate, but one I'm sure we have no control over. I don't see any merit in the kernel disallowing MAP_SYNC access on these platforms. Ideally, we'd have some way of ensuring older kernels don't work with these new platforms, but I don't think that's possible. Moving on to the patch itself--Aneesh, have you audited other persistent memory users in the kernel? For example, drivers/md/dm-writecache.c does this: static void writecache_commit_flushed(struct dm_writecache *wc, bool wait_for_ios) { if (WC_MODE_PMEM(wc)) wmb(); <========== else ssd_commit_flushed(wc, wait_for_ios); } I believe you'll need to make modifications there. Cheers, Jeff