From: "Madhavan T. Venkataraman" <email@example.com> To: Mark Brown <firstname.lastname@example.org> Cc: email@example.com, firstname.lastname@example.org, email@example.com, firstname.lastname@example.org, email@example.com, firstname.lastname@example.org, email@example.com, firstname.lastname@example.org, email@example.com, firstname.lastname@example.org Subject: Re: [RFC PATCH v3 3/4] arm64: Handle miscellaneous functions in .text and .init.text Date: Thu, 6 May 2021 10:30:21 -0500 [thread overview] Message-ID: <email@example.com> (raw) In-Reply-To: <20210506141211.GE4642@sirena.org.uk> On 5/6/21 9:12 AM, Mark Brown wrote: > On Mon, May 03, 2021 at 12:36:14PM -0500, firstname.lastname@example.org wrote: > >> There are some SYM_CODE functions that are currently in ".text" or >> ".init.text" sections. Some of these are functions that the unwinder >> does not care about as they are not "interesting" to livepatch. These >> will remain in their current sections. The rest I have moved into a >> new section called ".code.text". > > I was thinking it'd be good to do this by modifying SYM_CODE_START() to > emit the section, that way nobody can forget to put any SYM_CODE into a > special section. That does mean we'd have to first introduce a new > variant for specifying a section that lets us override things that need > to be in some specific section and convert everything that's in a > special section over to that first which is a bit annoying but feels > like it's worth it for the robustness. It'd also put some of the don't > cares into .code.text but so long as they are actually don't cares that > should be fine! > OK. I could make the section an argument to SYM_CODE*() so that a developer will never miss that. Some documentation may be in order so the guidelines are clear. I will do the doc patch separately, if that is alright with you all. About the don't car functions - most of them are OK to be moved into .code.text. But the hypervisor vector related code has a problem. I have not debugged that yet. If I add that code in .code.text, KVM initialization fails in one case. In another case, when I actually test with a VM, the VM does not come up. I am not sure. But it looks like there may be some reloc issue going on. I don't have a handle on this yet. So, for now, I will leave the hypervisor stuff in .text. But I will mark it as TBD in the cover letter so we don't lose track of it. >> Don't care functions >> ==================== > > We also have a bunch of things like __cpu_soft_restart which don't seem > to be called out here but need to be in .idmap.text. > It is already in .idmap.text. /* SPDX-License-Identifier: GPL-2.0-only */ /* * CPU reset routines * * Copyright (C) 2001 Deep Blue Solutions Ltd. * Copyright (C) 2012 ARM Ltd. * Copyright (C) 2015 Huawei Futurewei Technologies. */ #include <linux/linkage.h> #include <asm/assembler.h> #include <asm/sysreg.h> #include <asm/virt.h> .text .pushsection .idmap.text, "awx" /* * __cpu_soft_restart(el2_switch, entry, arg0, arg1, arg2) - Helper for * cpu_soft_restart. * * @el2_switch: Flag to indicate a switch to EL2 is needed. * @entry: Location to jump to for soft reset. * arg0: First argument passed to @entry. (relocation list) * arg1: Second argument passed to @entry.(physical kernel entry) * arg2: Third argument passed to @entry. (physical dtb address) * * Put the CPU into the same state as it would be if it had been reset, and * branch to what would be the reset vector. It must be executed with the * flat identity mapping. */ SYM_CODE_START(__cpu_soft_restart) mov_q x12, INIT_SCTLR_EL1_MMU_OFF pre_disable_mmu_workaround /* * either disable EL1&0 translation regime or disable EL2&0 translation * regime if HCR_EL2.E2H == 1 */ msr sctlr_el1, x12 isb cbz x0, 1f // el2_switch? mov x0, #HVC_SOFT_RESTART hvc #0 // no return 1: mov x8, x1 // entry mov x0, x2 // arg0 mov x1, x3 // arg1 mov x2, x4 // arg2 br x8 SYM_CODE_END(__cpu_soft_restart) .popsection I will double check all the *.S files and make sure that every function is accounted for in version 4. Stay tuned. Thanks. Madhavan
next prev parent reply other threads:[~2021-05-06 15:30 UTC|newest] Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top [not found] <65cf4dfbc439b010b50a0c46ec500432acde86d6> 2021-05-03 17:36 ` [RFC PATCH v3 0/4] arm64: Stack trace reliability checks in the unwinder madvenka 2021-05-03 17:36 ` [RFC PATCH v3 1/4] arm64: Introduce stack " madvenka 2021-05-04 15:50 ` Mark Brown 2021-05-04 19:14 ` Madhavan T. Venkataraman 2021-05-04 21:52 ` Josh Poimboeuf 2021-05-04 23:13 ` Madhavan T. Venkataraman 2021-05-05 0:07 ` Josh Poimboeuf 2021-05-05 0:21 ` Madhavan T. Venkataraman 2021-05-03 17:36 ` [RFC PATCH v3 2/4] arm64: Check the return PC against unreliable code sections madvenka 2021-05-04 16:05 ` Mark Brown 2021-05-04 19:03 ` Madhavan T. Venkataraman 2021-05-04 19:32 ` Madhavan T. Venkataraman 2021-05-05 16:46 ` Mark Brown 2021-05-05 18:48 ` Madhavan T. Venkataraman 2021-05-05 18:50 ` Madhavan T. Venkataraman 2021-05-06 13:45 ` Mark Brown 2021-05-06 15:21 ` Madhavan T. Venkataraman 2021-05-05 16:34 ` Mark Brown 2021-05-05 17:51 ` Madhavan T. Venkataraman 2021-05-05 19:30 ` Ard Biesheuvel 2021-05-05 20:00 ` Madhavan T. Venkataraman 2021-05-03 17:36 ` [RFC PATCH v3 3/4] arm64: Handle miscellaneous functions in .text and .init.text madvenka 2021-05-06 14:12 ` Mark Brown 2021-05-06 15:30 ` Madhavan T. Venkataraman [this message] 2021-05-06 15:32 ` Madhavan T. Venkataraman 2021-05-06 15:44 ` Mark Brown 2021-05-06 15:56 ` Madhavan T. Venkataraman 2021-05-06 15:37 ` Mark Brown 2021-05-06 15:57 ` Madhavan T. Venkataraman 2021-05-03 17:36 ` [RFC PATCH v3 4/4] arm64: Handle funtion graph tracer better in the unwinder madvenka 2021-05-06 14:43 ` Mark Brown 2021-05-06 15:20 ` Madhavan T. Venkataraman
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