From: "Jingoo Han" <jingoohan1@gmail.com>
To: "'Lorenzo Pieralisi'" <lorenzo.pieralisi@arm.com>,
<linux-pci@vger.kernel.org>
Cc: <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
"'Bjorn Helgaas'" <bhelgaas@google.com>,
"'Joao Pinto'" <Joao.Pinto@synopsys.com>
Subject: Re: [PATCH v4 14/21] PCI: designware: update PCI config space remap function
Date: Fri, 21 Apr 2017 18:02:54 -0400 [thread overview]
Message-ID: <000001d2baeb$07e84870$17b8d950$@gmail.com> (raw)
In-Reply-To: <20170419164913.19674-15-lorenzo.pieralisi@arm.com>
On Wednesday, April 19, 2017 12:49 PM, Lorenzo Pieralisi wrote:
>
> PCI configuration space should be mapped with a memory region type that
> generates on the CPU host bus non-posted write transations. Update the
> driver to use the devm_pci_remap_cfg* interface to make sure the correct
> memory mappings for PCI configuration space are used.
>
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Cc: Jingoo Han <jingoohan1@gmail.com>
Acked-by: Jingoo Han <jingoohan1@gmail.com>
Best regards,
Jingoo Han
> Cc: Joao Pinto <Joao.Pinto@synopsys.com>
> ---
> drivers/pci/dwc/pcie-designware-host.c | 12 +++++++-----
> 1 file changed, 7 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/pci/dwc/pcie-designware-host.c
> b/drivers/pci/dwc/pcie-designware-host.c
> index 5ba3349..2b789af 100644
> --- a/drivers/pci/dwc/pcie-designware-host.c
> +++ b/drivers/pci/dwc/pcie-designware-host.c
> @@ -338,8 +338,9 @@ int dw_pcie_host_init(struct pcie_port *pp)
> }
>
> if (!pci->dbi_base) {
> - pci->dbi_base = devm_ioremap(dev, pp->cfg->start,
> - resource_size(pp->cfg));
> + pci->dbi_base = devm_pci_remap_cfgspace(dev,
> + pp->cfg->start,
> + resource_size(pp->cfg));
> if (!pci->dbi_base) {
> dev_err(dev, "error with ioremap\n");
> ret = -ENOMEM;
> @@ -350,8 +351,8 @@ int dw_pcie_host_init(struct pcie_port *pp)
> pp->mem_base = pp->mem->start;
>
> if (!pp->va_cfg0_base) {
> - pp->va_cfg0_base = devm_ioremap(dev, pp->cfg0_base,
> - pp->cfg0_size);
> + pp->va_cfg0_base = devm_pci_remap_cfgspace(dev,
> + pp->cfg0_base, pp->cfg0_size);
> if (!pp->va_cfg0_base) {
> dev_err(dev, "error with ioremap in function\n");
> ret = -ENOMEM;
> @@ -360,7 +361,8 @@ int dw_pcie_host_init(struct pcie_port *pp)
> }
>
> if (!pp->va_cfg1_base) {
> - pp->va_cfg1_base = devm_ioremap(dev, pp->cfg1_base,
> + pp->va_cfg1_base = devm_pci_remap_cfgspace(dev,
> + pp->cfg1_base,
> pp->cfg1_size);
> if (!pp->va_cfg1_base) {
> dev_err(dev, "error with ioremap\n");
> --
> 2.10.0
next prev parent reply other threads:[~2017-04-21 22:03 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-04-19 16:48 [PATCH v4 00/21] PCI: fix config space memory mappings Lorenzo Pieralisi
2017-04-19 16:48 ` [PATCH v4 01/21] PCI: remove __weak tag from pci_remap_iospace() Lorenzo Pieralisi
2017-04-19 16:48 ` [PATCH v4 02/21] linux/io.h: add PCI config space remap interface Lorenzo Pieralisi
2017-04-20 10:51 ` Lorenzo Pieralisi
2017-04-20 13:12 ` Bjorn Helgaas
2017-04-19 16:48 ` [PATCH v4 03/21] ARM64: implement pci_remap_cfgspace() interface Lorenzo Pieralisi
2017-04-20 10:33 ` Catalin Marinas
2017-04-19 16:48 ` [PATCH v4 04/21] ARM: " Lorenzo Pieralisi
2017-04-19 16:48 ` [PATCH v4 05/21] lib: fix Devres devm_ioremap_* offset parameter kerneldoc description Lorenzo Pieralisi
2017-04-28 21:20 ` Tejun Heo
2017-04-19 16:48 ` [PATCH v4 06/21] PCI: implement Devres interface to map PCI config space Lorenzo Pieralisi
2017-04-19 16:48 ` [PATCH v4 07/21] PCI: ECAM: use pci_remap_cfgspace() to map config region Lorenzo Pieralisi
2017-04-19 16:48 ` [PATCH v4 08/21] PCI: xilinx: update PCI config space remap function Lorenzo Pieralisi
2017-04-19 16:48 ` [PATCH v4 09/21] PCI: xilinx-nwl: " Lorenzo Pieralisi
2017-04-19 16:48 ` [PATCH v4 10/21] PCI: spear13xx: " Lorenzo Pieralisi
2017-04-19 16:49 ` [PATCH v4 11/21] PCI: rockchip: " Lorenzo Pieralisi
2017-04-19 16:49 ` [PATCH v4 12/21] PCI: qcom: " Lorenzo Pieralisi
2017-04-19 16:49 ` [PATCH v4 13/21] PCI: iproc-platform: " Lorenzo Pieralisi
2017-04-19 16:49 ` [PATCH v4 14/21] PCI: designware: " Lorenzo Pieralisi
2017-04-21 22:02 ` Jingoo Han [this message]
2017-04-19 16:49 ` [PATCH v4 15/21] PCI: armada8k: " Lorenzo Pieralisi
2017-04-19 16:49 ` [PATCH v4 16/21] PCI: xgene: " Lorenzo Pieralisi
2017-04-19 16:49 ` [PATCH v4 17/21] PCI: tegra: " Lorenzo Pieralisi
2017-04-19 16:49 ` [PATCH v4 18/21] PCI: hisi: " Lorenzo Pieralisi
2017-04-19 16:49 ` [PATCH v4 19/21] PCI: layerscape: " Lorenzo Pieralisi
2017-04-19 16:49 ` [PATCH v4 20/21] PCI: keystone-dw: " Lorenzo Pieralisi
2017-04-19 16:49 ` [PATCH v4 21/21] PCI: versatile: " Lorenzo Pieralisi
2017-04-20 13:25 ` [PATCH v4 00/21] PCI: fix config space memory mappings Bjorn Helgaas
2017-04-25 6:40 ` Jon Masters
2017-04-25 16:20 ` Jingoo Han
2017-04-25 18:31 ` Khuong Dinh
2017-04-26 10:53 ` Dongdong Liu
2017-04-26 17:24 ` Jingoo Han
2017-04-27 1:46 ` Dongdong Liu
2017-04-27 16:42 ` Khuong Dinh
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='000001d2baeb$07e84870$17b8d950$@gmail.com' \
--to=jingoohan1@gmail.com \
--cc=Joao.Pinto@synopsys.com \
--cc=bhelgaas@google.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).