From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932872AbcLIHu5 (ORCPT ); Fri, 9 Dec 2016 02:50:57 -0500 Received: from mga03.intel.com ([134.134.136.65]:47183 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752861AbcLIHuy (ORCPT ); Fri, 9 Dec 2016 02:50:54 -0500 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,323,1477983600"; d="scan'208";a="40748591" From: "Tan, Jui Nee" To: Andy Shevchenko CC: "mika.westerberg@linux.intel.com" , "heikki.krogerus@linux.intel.com" , "tglx@linutronix.de" , "dvhart@infradead.org" , "mingo@redhat.com" , "hpa@zytor.com" , "x86@kernel.org" , "ptyser@xes-inc.com" , "lee.jones@linaro.org" , "linus.walleij@linaro.org" , "linux-gpio@vger.kernel.org" , "platform-driver-x86@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "Yong, Jonathan" , "Yu, Ong Hock" , "Luck, Tony" , "Wan Mohamad, Wan Ahmad Zainie" , "Sun, Yunying" Subject: RE: [PATCH v10 1/6] drivers/platform/x86/p2sb: New Primary to Sideband bridge support driver for Intel SOC's Thread-Topic: [PATCH v10 1/6] drivers/platform/x86/p2sb: New Primary to Sideband bridge support driver for Intel SOC's Thread-Index: AQHSOzEKscNNPC2tkUGWm4eea3uibaDR3IQAgC2JtHA= Date: Fri, 9 Dec 2016 07:50:48 +0000 Message-ID: <0158A29DB680F54A88142ED28D55B1D008329343@PGSMSX107.gar.corp.intel.com> References: <1478768430-13422-1-git-send-email-jui.nee.tan@intel.com> <1478768430-13422-2-git-send-email-jui.nee.tan@intel.com> <1478794036.5295.130.camel@linux.intel.com> In-Reply-To: <1478794036.5295.130.camel@linux.intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [172.30.20.206] Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id uB97p28h013474 > -----Original Message----- > From: linux-gpio-owner@vger.kernel.org [mailto:linux-gpio- > owner@vger.kernel.org] On Behalf Of Andy Shevchenko > Sent: Friday, November 11, 2016 12:07 AM > To: Tan, Jui Nee ; mika.westerberg@linux.intel.com; > heikki.krogerus@linux.intel.com; tglx@linutronix.de; dvhart@infradead.org; > mingo@redhat.com; hpa@zytor.com; x86@kernel.org; ptyser@xes-inc.com; > lee.jones@linaro.org; linus.walleij@linaro.org > Cc: linux-gpio@vger.kernel.org; platform-driver-x86@vger.kernel.org; > linux-kernel@vger.kernel.org; Yong, Jonathan ; > Yu, Ong Hock ; Luck, Tony ; > Wan Mohamad, Wan Ahmad Zainie ; > Sun, Yunying > Subject: Re: [PATCH v10 1/6] drivers/platform/x86/p2sb: New Primary to > Sideband bridge support driver for Intel SOC's > > On Thu, 2016-11-10 at 17:00 +0800, Tan Jui Nee wrote: > > From: Andy Shevchenko > > > > There is already one and at least one more user coming which require > > an access to Primary to Sideband bridge (P2SB) in order to get IO or > > MMIO bar hidden by BIOS. > > Create a driver to access P2SB for x86 devices. > > > > Signed-off-by: Yong, Jonathan > > Signed-off-by: Andy Shevchenko > > > > +int p2sb_bar(struct pci_dev *pdev, unsigned int devfn, > > + struct resource *res) > > +{ > > + u32 base_addr; > > + u64 base64_addr; > > + unsigned long flags; > > + > > > > > + if (!res) > > + return -EINVAL; > > I don't remember the details, one version was quite changed, so, I think > these lines are not needed anymore. > Noted, these lines will be removed in next patch version (v12). > > + /* Get IO or MMIO BAR */ > > + pci_bus_read_config_dword(pdev->bus, devfn, SBREG_BAR, > > &base_addr); > > + if ((base_addr & PCI_BASE_ADDRESS_SPACE) == > > PCI_BASE_ADDRESS_SPACE_IO) { > > + flags = IORESOURCE_IO; > > + base64_addr = base_addr & PCI_BASE_ADDRESS_IO_MASK; > > + } else { > > + flags = IORESOURCE_MEM; > > + base64_addr = base_addr & PCI_BASE_ADDRESS_MEM_MASK; > > + if (base_addr & PCI_BASE_ADDRESS_MEM_TYPE_64) { > > + flags |= IORESOURCE_MEM_64; > > > > > + pci_bus_read_config_dword(pdev->bus, devfn, > > + SBREG_BAR + 4, &base_addr); > > Fix indentation. > Thanks for pointing that out. I will fix that in next patch version (v12). > > + base64_addr |= (u64)base_addr << 32; > > + } > > + } > > + > > + /* Hide the P2SB device */ > > + pci_bus_write_config_byte(pdev->bus, devfn, SBREG_HIDE, > > 0x01); > > + > > + spin_unlock(&p2sb_spinlock); > > + > > > + /* User provides prefilled resources */ > > Not anymore as far I as I can see. You just return here the result. > Current version is returning status of p2sb_bar function, i.e., 0 on success or appropriate errno value on error. Perhaps you could share the reason of return the result instead of status. > > + res->start = (resource_size_t)base64_addr; > > + res->flags = flags; > > -- > Andy Shevchenko > Intel Finland Oy > -- > To unsubscribe from this list: send the line "unsubscribe linux-gpio" in > the body of a message to majordomo@vger.kernel.org More majordomo info at > http://vger.kernel.org/majordomo-info.html