From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752022AbdAMPFI (ORCPT ); Fri, 13 Jan 2017 10:05:08 -0500 Received: from mail-lf0-f68.google.com ([209.85.215.68]:35475 "EHLO mail-lf0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750768AbdAMPFF (ORCPT ); Fri, 13 Jan 2017 10:05:05 -0500 Subject: Re: [PATCH v2 2/6] arm: dts: mt2701: Add iommu/smi device node To: Erin Lo References: <1484296978-18572-1-git-send-email-erin.lo@mediatek.com> <1484296978-18572-3-git-send-email-erin.lo@mediatek.com> Cc: srv_heupstream@mediatek.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, Honghui Zhang From: Matthias Brugger Message-ID: <02062506-f917-0140-4934-31d7d3317b80@gmail.com> Date: Fri, 13 Jan 2017 16:05:01 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.6.0 MIME-Version: 1.0 In-Reply-To: <1484296978-18572-3-git-send-email-erin.lo@mediatek.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Erin, I just took the patch from Honghui he send in june. Please see my comment inline. On 13/01/17 09:42, Erin Lo wrote: > From: Honghui Zhang > > Add the device node of iommu and smi for MT2701. > > Signed-off-by: Honghui Zhang > Signed-off-by: Erin Lo > --- > arch/arm/boot/dts/mt2701.dtsi | 54 +++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 54 insertions(+) > > diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi > index eb4c6fd..87be52c 100644 > --- a/arch/arm/boot/dts/mt2701.dtsi > +++ b/arch/arm/boot/dts/mt2701.dtsi > @@ -17,6 +17,7 @@ > #include > #include > #include > +#include > #include "skeleton64.dtsi" > #include "mt2701-pinfunc.h" > > @@ -161,6 +162,16 @@ > clock-names = "system-clk", "rtc-clk"; > }; > > + smi_common: smi@1000c000 { > + compatible = "mediatek,mt2701-smi-common"; > + reg = <0 0x1000c000 0 0x1000>; > + clocks = <&infracfg CLK_INFRA_SMI>, > + <&mmsys CLK_MM_SMI_COMMON>, > + <&infracfg CLK_INFRA_SMI>; > + clock-names = "apb", "smi", "async"; > + power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; > + }; > + > sysirq: interrupt-controller@10200100 { > compatible = "mediatek,mt2701-sysirq", > "mediatek,mt6577-sysirq"; > @@ -170,6 +181,16 @@ > reg = <0 0x10200100 0 0x1c>; > }; > > + iommu: mmsys_iommu@10205000 { > + compatible = "mediatek,mt2701-m4u"; > + reg = <0 0x10205000 0 0x1000>; > + interrupts = ; > + clocks = <&infracfg CLK_INFRA_M4U>; > + clock-names = "bclk"; > + mediatek,larbs = <&larb0 &larb1 &larb2>; > + #iommu-cells = <1>; > + }; > + > apmixedsys: syscon@10209000 { > compatible = "mediatek,mt2701-apmixedsys", "syscon"; > reg = <0 0x10209000 0 0x1000>; > @@ -272,18 +293,51 @@ > #clock-cells = <1>; > }; > > + larb0: larb@14010000 { > + compatible = "mediatek,mt2701-smi-larb"; > + reg = <0 0x14010000 0 0x1000>; > + mediatek,smi = <&smi_common>; > + mediatek,larbidx = <0>; Did I miss something? 'mediatek,larbidx' does not sound familiar to me. Regards, Matthias > + clocks = <&mmsys CLK_MM_SMI_LARB0>, > + <&mmsys CLK_MM_SMI_LARB0>; > + clock-names = "apb", "smi"; > + power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; > + }; > + > imgsys: syscon@15000000 { > compatible = "mediatek,mt2701-imgsys", "syscon"; > reg = <0 0x15000000 0 0x1000>; > #clock-cells = <1>; > }; > > + larb2: larb@15001000 { > + compatible = "mediatek,mt2701-smi-larb"; > + reg = <0 0x15001000 0 0x1000>; > + mediatek,smi = <&smi_common>; > + mediatek,larbidx = <2>; > + clocks = <&imgsys CLK_IMG_SMI_COMM>, > + <&imgsys CLK_IMG_SMI_COMM>; > + clock-names = "apb", "smi"; > + power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; > + }; > + > vdecsys: syscon@16000000 { > compatible = "mediatek,mt2701-vdecsys", "syscon"; > reg = <0 0x16000000 0 0x1000>; > #clock-cells = <1>; > }; > > + larb1: larb@16010000 { > + compatible = "mediatek,mt2701-smi-larb"; > + reg = <0 0x16010000 0 0x1000>; > + mediatek,smi = <&smi_common>; > + mediatek,larbidx = <1>; > + clocks = <&vdecsys CLK_VDEC_CKGEN>, > + <&vdecsys CLK_VDEC_LARB>; > + clock-names = "apb", "smi"; > + power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>; > + }; > + > hifsys: syscon@1a000000 { > compatible = "mediatek,mt2701-hifsys", "syscon"; > reg = <0 0x1a000000 0 0x1000>; >